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Message-ID: <20250617160103-mutt-send-email-mst@kernel.org>
Date: Tue, 17 Jun 2025 16:01:53 -0400
From: "Michael S. Tsirkin" <mst@...hat.com>
To: Jason Gunthorpe <jgg@...pe.ca>
Cc: Demi Marie Obenour <demiobenour@...il.com>,
Jason Wang <jasowang@...hat.com>,
Xuan Zhuo <xuanzhuo@...ux.alibaba.com>,
Eugenio Pérez <eperezma@...hat.com>,
"Rafael J. Wysocki" <rafael@...nel.org>,
Len Brown <lenb@...nel.org>, Thomas Gleixner <tglx@...utronix.de>,
Ingo Molnar <mingo@...hat.com>, Borislav Petkov <bp@...en8.de>,
Dave Hansen <dave.hansen@...ux.intel.com>,
"H. Peter Anvin" <hpa@...or.com>, Joerg Roedel <joro@...tes.org>,
Will Deacon <will@...nel.org>, Robin Murphy <robin.murphy@....com>,
Alyssa Ross <hi@...ssa.is>, virtualization@...ts.linux.dev,
linux-kernel@...r.kernel.org, linux-acpi@...r.kernel.org,
iommu@...ts.linux.dev, x86@...nel.org,
Spectrum OS Development <devel@...ctrum-os.org>
Subject: Re: Virtio-IOMMU interrupt remapping design
On Tue, Jun 17, 2025 at 04:57:20PM -0300, Jason Gunthorpe wrote:
> On Tue, Jun 17, 2025 at 03:44:20PM -0400, Michael S. Tsirkin wrote:
> > On Mon, Jun 16, 2025 at 10:20:31AM -0300, Jason Gunthorpe wrote:
> > > On Sun, Jun 15, 2025 at 02:47:15PM -0400, Demi Marie Obenour wrote:
> > >
> > > > Is a paravirtualized IOMMU with interrupt remapping something that makes
> > > > sense?
> > >
> > > IMHO linking interrupt remapping to the iommu is a poor design,
> > > interrupt routing belongs in the irq subsystem, not in the iommu.
> > >
> > > The fact AMD and Intel both coupled their interrupt routing to their
> > > iommu hardware is just a weird design decision. ARM didn't do this,
> > > for instance.
> >
> > why does it matter in which device it resides?
>
> It would cleanup the boot process if the IRQ components were available
> at the same time as the IRQ drivers instead of much later when the
> iommu gets plugged in.
>
> > Way I see it, there is little reason to remap interrupts without
> > also using an iommu, so why not a single device. what did I miss?
>
> Remapping interrupts can be understood to be virtualizing the MSI
> addr/data pair space so that the CPU controls where the interrupt goes
> though its internal tables not the device through the addr/data.
>
> On x86 you also need to use remapping to exceed the max CPU count that
> can be encoded in the MSI, no iommu required to need this.
More of an x86 quirk though, isn't it?
> There is also some stuff related to IMS that could get improved here.
>
> You don't need an iommu to enjoy those benefits.
>
> Jason
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