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Message-ID: <145c8616-d595-4caf-980d-20eadc39d0bd@163.com>
Date: Wed, 18 Jun 2025 22:24:12 +0800
From: Hans Zhang <18255117159@....com>
To: Manivannan Sadhasivam <mani@...nel.org>
Cc: bhelgaas@...gle.com, lpieralisi@...nel.org, kw@...ux.com,
krzk+dt@...nel.org, manivannan.sadhasivam@...aro.org, conor+dt@...nel.org,
robh@...nel.org, linux-pci@...r.kernel.org, linux-kernel@...r.kernel.org,
devicetree@...r.kernel.org
Subject: Re: [PATCH v2 3/3] PCI: of: Relax max-link-speed check to support
PCIe Gen5/Gen6
On 2025/6/18 00:50, Manivannan Sadhasivam wrote:
> On Thu, May 29, 2025 at 10:10:26AM +0800, Hans Zhang wrote:
>> The existing code restricted `max-link-speed` to values 1~4 (Gen1~Gen4),
>> but current SOCs using Synopsys/Cadence IP may require Gen5/Gen6 support.
>> This patch updates the validation in `of_pci_get_max_link_speed` to allow
>> values up to 6, ensuring compatibility with newer PCIe generations.
>>
>> Signed-off-by: Hans Zhang <18255117159@....com>
>
> DT binding validation should be sufficient. But still...
>
> Reviewed-by: Manivannan Sadhasivam <mani@...nel.org>
>
Dear Maniļ¼
Thank you very much for your review.
Best regards,
Hans
> - Mani
>
>> ---
>> drivers/pci/of.c | 2 +-
>> 1 file changed, 1 insertion(+), 1 deletion(-)
>>
>> diff --git a/drivers/pci/of.c b/drivers/pci/of.c
>> index ab7a8252bf41..379d90913937 100644
>> --- a/drivers/pci/of.c
>> +++ b/drivers/pci/of.c
>> @@ -890,7 +890,7 @@ int of_pci_get_max_link_speed(struct device_node *node)
>> u32 max_link_speed;
>>
>> if (of_property_read_u32(node, "max-link-speed", &max_link_speed) ||
>> - max_link_speed == 0 || max_link_speed > 4)
>> + max_link_speed == 0 || max_link_speed > 6)
>> return -EINVAL;
>>
>> return max_link_speed;
>> --
>> 2.25.1
>>
>
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