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Message-ID: <3305378C-7D27-4A89-9DF8-B7F1A1582613@zytor.com>
Date: Tue, 17 Jun 2025 20:34:17 -0700
From: "H. Peter Anvin" <hpa@...or.com>
To: Xin Li <xin@...or.com>, Sean Christopherson <seanjc@...gle.com>
CC: linux-kernel@...r.kernel.org, kvm@...r.kernel.org, tglx@...utronix.de,
mingo@...hat.com, bp@...en8.de, dave.hansen@...ux.intel.com,
x86@...nel.org, pbonzini@...hat.com, peterz@...radead.org,
sohil.mehta@...el.com, brgerst@...il.com, tony.luck@...el.com,
fenghuay@...dia.com
Subject: Re: [PATCH v2 2/2] x86/traps: Initialize DR7 by writing its architectural reset value
On June 17, 2025 5:15:18 PM PDT, Xin Li <xin@...or.com> wrote:
>On 6/17/2025 4:08 PM, Xin Li wrote:
>>
>> I hope the bit will be kept reserved to 1 *forever*, because inverted
>> polarity seems causing confusing and complicated code only.
>
>BTW, FRED flipped BLD and RTM polarities in its event data:
>
>The event data is not exactly the same as that which will be in DR6
>following delivery of the #DB. The polarity of bit 11 (BLD) and bit 16
>(RTM) is inverted in DR6.
>
>
>I.e., BLD and RTM are active high in FRED event data.
Yes, we designed it so FRED (and VTx) are always active high
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