linux-kernel - RE: [PATCH 1/2] x86/mce: Fix missing address mask in recovery for errors in TDX/SEAM non-root mode

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Message-ID: <SJ1PR11MB6083E80CEE14BA99F7A0E237FC72A@SJ1PR11MB6083.namprd11.prod.outlook.com>
Date: Wed, 18 Jun 2025 23:46:45 +0000
From: "Luck, Tony" <tony.luck@...el.com>
To: "Huang, Kai" <kai.huang@...el.com>, "pbonzini@...hat.com"
	<pbonzini@...hat.com>, "Hunter, Adrian" <adrian.hunter@...el.com>,
	"seanjc@...gle.com" <seanjc@...gle.com>
CC: "kvm@...r.kernel.org" <kvm@...r.kernel.org>, "Li, Xiaoyao"
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	"dave.hansen@...ux.intel.com" <dave.hansen@...ux.intel.com>,
	"tony.lindgren@...ux.intel.com" <tony.lindgren@...ux.intel.com>,
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 Vishal" <vannapurve@...gle.com>, "Edgecombe, Rick P"
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Subject: RE: [PATCH 1/2] x86/mce: Fix missing address mask in recovery for
 errors in TDX/SEAM non-root mode

> It's sort of hinted at in the SDM Vol 3B Figure 17-7. IA32_MCi_ADDR MSR
> with the footnote in the diagram:
>
>   "Useful bits in this field depend on the address methodology in use when the
>    the register state is saved."
>
> Maybe there is something more explicit in documentation for memory encryption?


Section 5.1 in 
https://software.intel.com/sites/default/files/managed/a5/16/Multi-Key-Total-Memory-Encryption-Spec.pdf

shows how the upper bits of the physical address are used for the :KeyID"

-Tony