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Message-ID: <a6cd3756-5aa7-435f-9ee7-3fde67c29f17@linux.intel.com>
Date: Thu, 19 Jun 2025 10:33:01 -0400
From: "Liang, Kan" <kan.liang@...ux.intel.com>
To: tanze <tanze@...inos.cn>, peterz@...radead.org
Cc: linux-perf-users@...r.kernel.org, linux-kernel@...r.kernel.org,
x86@...nel.org
Subject: Re: [PATCH] perf/x86/zhaoxin: Fix instructions error by missing
fixedctr member
On 2025-06-18 11:19 p.m., tanze wrote:
> Perf's instructions event tests on Zhaoxin CPUs may exhibit:
>
> $perf stat -e instructions,cycles ls -l
>
> ......
> Performance counter stats for 'ls -l':
>
> 0 instructions # 0.00 insn per cycle
> 9,488,278 cycles
>
> 0.004365407 seconds time elapsed
>
> 0.003303000 seconds user
> 0.001099000 seconds sys
>
> The absence of the fixedctr member leads to an incorrect hwc->event_base
> value on Zhaoxin CPUs, causing a discrepancy in the instruction count
> reported by perf stat. This commit resolves the instruction count issue
> by properly initializing the fixedctr member.
>
> Fixes: 149fd4712bcd ("perf/x86/intel: Support Perfmon MSRs aliasing")
>
Please remove the empty line.
> Signed-off-by: tanze <tanze@...inos.cn>
I have no idea Zhaoxin also have fixed counters.
If so, Yes, I think the patch is required.
Reviewed-by: Kan Liang <kan.liang@...ux.intel.com>
Thanks,
Kan> ---
> arch/x86/events/zhaoxin/core.c | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/arch/x86/events/zhaoxin/core.c b/arch/x86/events/zhaoxin/core.c
> index 4bdfcf091200..3fc3f9abece9 100644
> --- a/arch/x86/events/zhaoxin/core.c
> +++ b/arch/x86/events/zhaoxin/core.c
> @@ -467,6 +467,7 @@ static const struct x86_pmu zhaoxin_pmu __initconst = {
> .schedule_events = x86_schedule_events,
> .eventsel = MSR_ARCH_PERFMON_EVENTSEL0,
> .perfctr = MSR_ARCH_PERFMON_PERFCTR0,
> + .fixedctr = MSR_ARCH_PERFMON_FIXED_CTR0,
> .event_map = zhaoxin_pmu_event_map,
> .max_events = ARRAY_SIZE(zx_pmon_event_map),
> .apic = 1,
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