linux-kernel - Re: [PATCH v2] arm64: dts: ti: k3-am642-evm-pcie0-ep: Add boot phase tag to "pcie0

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Message-ID: <28c88a78-fe34-4595-b260-c6cc40897bc1@ti.com>
Date: Thu, 19 Jun 2025 13:25:43 +0530
From: Vignesh Raghavendra <vigneshr@...com>
To: Hrushikesh Salunke <h-salunke@...com>, <nm@...com>, <kristo@...nel.org>,
        <robh@...nel.org>, <krzk+dt@...nel.org>, <conor+dt@...nel.org>
CC: <s-vadapalli@...com>, <linux-arm-kernel@...ts.infradead.org>,
        <devicetree@...r.kernel.org>, <linux-kernel@...r.kernel.org>,
        <danishanwar@...com>
Subject: Re: [PATCH v2] arm64: dts: ti: k3-am642-evm-pcie0-ep: Add boot phase
 tag to "pcie0_ep"



On 12/06/25 15:46, Hrushikesh Salunke wrote:
> 
> 
> On 11/06/25 14:17, Hrushikesh Salunke wrote:
>>
>>
>> On 11/06/25 14:14, Vignesh Raghavendra wrote:
>>>
>>>
>>> On 10/06/25 11:19, Hrushikesh Salunke wrote:
>>>> AM64X SoC has one instance of PCIe which is PCIe0. To support PCIe boot
>>>> on AM64X SoC, PCIe0 needs to be in endpoint mode and it needs to be
>>>> functional at all stages of PCIe boot process. Thus add the
>>>> "bootph-all" boot phase tag to "pcie0_ep" device tree node.
>>>>
>>>> Signed-off-by: Hrushikesh Salunke <h-salunke@...com>
>>>> ---
>>>> This patch is based on commit
>>>> 475c850a7fdd Add linux-next specific files for 20250606
>>>>
>>>> Changes since v1
>>>> As per feedback from Nishanth, changed the position of "bootph-all"
>>>> tag, according to ordering rules for device tree properties.
>>>>
>>>> v1 : https://lore.kernel.org/
>>>> all/20250609115930.w2s6jzg7xii55dlu@...ckled/
>>>>
>>>>   arch/arm64/boot/dts/ti/k3-am642-evm-pcie0-ep.dtso | 1 +
>>>>   1 file changed, 1 insertion(+)
>>>>
>>>> diff --git a/arch/arm64/boot/dts/ti/k3-am642-evm-pcie0-ep.dtso b/
>>>> arch/arm64/boot/dts/ti/k3-am642-evm-pcie0-ep.dtso
>>>> index 432751774853..a7e8d4ea98ac 100644
>>>> --- a/arch/arm64/boot/dts/ti/k3-am642-evm-pcie0-ep.dtso
>>>> +++ b/arch/arm64/boot/dts/ti/k3-am642-evm-pcie0-ep.dtso
>>>> @@ -46,6 +46,7 @@ pcie0_ep: pcie-ep@...2000 {
>>>>           max-functions = /bits/ 8 <1>;
>>>>           phys = <&serdes0_pcie_link>;
>>>>           phy-names = "pcie-phy";
>>>> +        bootph-all;
>>>>           ti,syscon-pcie-ctrl = <&pcie0_ctrl 0x0>;
>>>>       };
>>>>   };
>>>
>>> Are the patches for PCIe boot support merged to U-Boot or such other
>>> bootloader repo?
>>> No, they are not in the U-Boot yet. I will be posting patches for PCIe
>> boot support for U-Boot this week.
>>
> 
> I have posted Patch series for the PCIe boot support in Uboot.


Great, but dont you need bootph-all in dependent nodes as well such as
serdes0_pcie_link pcie0_ctrl? how does this work otherwise?

> 
> 1.https://patchwork.ozlabs.org/project/uboot/
> patch/20250612084910.3457060-1-h-salunke@...com/
> 2. https://patchwork.ozlabs.org/project/uboot/
> cover/20250612085023.3457117-1-h-salunke@...com/
> 3. https://patchwork.ozlabs.org/project/uboot/
> cover/20250612085534.3457522-1-h-salunke@...com/
> 
> 
> Regards,
> Hrushikesh.

-- 
Regards
Vignesh
https://ti.com/opensource