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Message-ID: <CAPYmKFvcnDJWXAUEX8oY6seQrgwKiZjDqrJ_R2rJ4kWq7RQUSg@mail.gmail.com>
Date: Sun, 22 Jun 2025 18:11:49 +0800
From: Xu Lu <luxu.kernel@...edance.com>
To: Radim Krčmář <rkrcmar@...tanamicro.com>
Cc: anup@...infault.org, atish.patra@...ux.dev, paul.walmsley@...ive.com, 
	palmer@...belt.com, aou@...s.berkeley.edu, alex@...ti.fr, kvm@...r.kernel.org, 
	kvm-riscv@...ts.infradead.org, linux-riscv@...ts.infradead.org, 
	linux-kernel@...r.kernel.org, 
	linux-riscv <linux-riscv-bounces@...ts.infradead.org>
Subject: Re: [External] Re: [PATCH] RISC-V: KVM: Delegate illegal instruction fault

Hi Radim,

On Fri, Jun 20, 2025 at 8:04 PM Radim Krčmář <rkrcmar@...tanamicro.com> wrote:
>
> 2025-06-20T17:17:20+08:00, Xu Lu <luxu.kernel@...edance.com>:
> > Delegate illegal instruction fault to VS mode in default to avoid such
> > exceptions being trapped to HS and redirected back to VS.
> >
> > Signed-off-by: Xu Lu <luxu.kernel@...edance.com>
> > ---
> > diff --git a/arch/riscv/include/asm/kvm_host.h b/arch/riscv/include/asm/kvm_host.h
> > @@ -48,6 +48,7 @@
> > +                                      BIT(EXC_INST_ILLEGAL)    | \
>
> You should also remove the dead code in kvm_riscv_vcpu_exit.

I only want to delegate it by default. And KVM may still want to
delegate different exceptions for different VMs like what it does for
EXC_BREAKPOINT. So maybe it is better to reserve these codes?

>
> And why not delegate the others as well?
> (EXC_LOAD_MISALIGNED, EXC_STORE_MISALIGNED, EXC_LOAD_ACCESS,
>  EXC_STORE_ACCESS, and EXC_INST_ACCESS.)

Thanks for the reminder. I will have a test and resend the patch if it works.

>
> Thanks.

Best Regards,
Xu Lu

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