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Message-ID: <8f6effaf-0a4b-411e-8e12-57f3c83069c2@linux.intel.com>
Date: Mon, 23 Jun 2025 09:17:23 +0800
From: "Mi, Dapeng" <dapeng1.mi@...ux.intel.com>
To: Peter Zijlstra <peterz@...radead.org>
Cc: Ingo Molnar <mingo@...hat.com>, Arnaldo Carvalho de Melo
<acme@...nel.org>, Namhyung Kim <namhyung@...nel.org>,
Ian Rogers <irogers@...gle.com>, Adrian Hunter <adrian.hunter@...el.com>,
Alexander Shishkin <alexander.shishkin@...ux.intel.com>,
Kan Liang <kan.liang@...ux.intel.com>, Andi Kleen <ak@...ux.intel.com>,
Eranian Stephane <eranian@...gle.com>, linux-kernel@...r.kernel.org,
linux-perf-users@...r.kernel.org, Dapeng Mi <dapeng1.mi@...el.com>
Subject: Re: [Patch v4 07/13] perf/x86/intel: Allocate arch-PEBS buffer and
initialize PEBS_BASE MSR
On 6/21/2025 5:20 PM, Peter Zijlstra wrote:
> On Fri, Jun 20, 2025 at 10:39:03AM +0000, Dapeng Mi wrote:
>
>> diff --git a/arch/x86/events/intel/ds.c b/arch/x86/events/intel/ds.c
>> index b6eface4dccd..72b925b8c482 100644
>> --- a/arch/x86/events/intel/ds.c
>> +++ b/arch/x86/events/intel/ds.c
>> @@ -625,13 +625,22 @@ static int alloc_pebs_buffer(int cpu)
>> int max, node = cpu_to_node(cpu);
>> void *buffer, *insn_buff, *cea;
>>
>> - if (!x86_pmu.ds_pebs)
>> + if (!intel_pmu_has_pebs())
>> return 0;
>>
>> - buffer = dsalloc_pages(bsiz, GFP_KERNEL, cpu);
>> + /*
>> + * alloc_pebs_buffer() could be called by init_arch_pebs_buf_on_cpu()
>> + * which is in atomic context.
>> + */
>> + buffer = dsalloc_pages(bsiz, preemptible() ? GFP_KERNEL : GFP_ATOMIC, cpu);
>> if (unlikely(!buffer))
>> return -ENOMEM;
> Here we go again.. that is CPU_STARTING context, that has IRQs disabled
> and as such no allocation is allowed. Not even GFP_ATOMIC -- this will
> break PREEMPT_RT.
Thanks. So we could have to follow what current legacy PEBS does and defer
the PEBS buffer allocation until creating perf events
(x86_reserve_hardware()).
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