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Message-ID: <b21b9865-7344-45ab-8f03-09cbd8b961b5@collabora.com>
Date: Mon, 23 Jun 2025 14:28:06 +0200
From: AngeloGioacchino Del Regno <angelogioacchino.delregno@...labora.com>
To: Krzysztof Kozlowski <krzk@...nel.org>, Laura Nao
<laura.nao@...labora.com>, mturquette@...libre.com, sboyd@...nel.org,
robh@...nel.org, krzk+dt@...nel.org, conor+dt@...nel.org,
matthias.bgg@...il.com, p.zabel@...gutronix.de, richardcochran@...il.com
Cc: guangjie.song@...iatek.com, wenst@...omium.org,
linux-clk@...r.kernel.org, devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
linux-mediatek@...ts.infradead.org, netdev@...r.kernel.org,
kernel@...labora.com
Subject: Re: [PATCH 09/30] dt-bindings: clock: mediatek: Describe MT8196
peripheral clock controllers
Il 23/06/25 14:12, Krzysztof Kozlowski ha scritto:
> On 23/06/2025 12:29, Laura Nao wrote:
>> +properties:
>> + compatible:
>> + items:
>> + - enum:
>> + - mediatek,mt8196-adsp
>> + - mediatek,mt8196-imp-iic-wrap-c
>> + - mediatek,mt8196-imp-iic-wrap-e
>> + - mediatek,mt8196-imp-iic-wrap-n
>> + - mediatek,mt8196-imp-iic-wrap-w
>> + - mediatek,mt8196-mdpsys0
>> + - mediatek,mt8196-mdpsys1
>> + - mediatek,mt8196-pericfg-ao
>> + - mediatek,mt8196-pextp0cfg-ao
>> + - mediatek,mt8196-pextp1cfg-ao
>> + - mediatek,mt8196-ufscfg-ao
>> + - mediatek,mt8196-vencsys
>> + - mediatek,mt8196-vencsys-c1
>> + - mediatek,mt8196-vencsys-c2
>> + - mediatek,mt8196-vdecsys
>> + - mediatek,mt8196-vdecsys-soc
>> + - const: syscon
>
> Why everything is syscon?
>
>
>> +
>> + reg:
>> + maxItems: 1
>> +
>> + '#clock-cells':
>> + const: 1
>> +
>> + '#reset-cells':
>> + const: 1
>> +
>> + mediatek,hardware-voter:
>> + $ref: /schemas/types.yaml#/definitions/phandle
>> + description: A phandle of the hw voter node
>> +
>> +required:
>> + - compatible
>> + - reg
>> + - '#clock-cells'
>> +
>> +additionalProperties: false
>> +
>> +examples:
>> + - |
>> + pericfg_ao: clock-controller@...40000 {
>> + compatible = "mediatek,mt8196-pericfg-ao", "syscon";
>> + reg = <0x16640000 0x1000>;
>> + mediatek,hardware-voter = <&scp_hwv>;
>> + #clock-cells = <1>;
>> + };
>> + - |
>> + pextp0cfg_ao: clock-controller@...b0000 {
>> + compatible = "mediatek,mt8196-pextp0cfg-ao", "syscon";
>> + reg = <0x169b0000 0x1000>;
>> + #clock-cells = <1>;
>> + #reset-cells = <1>;
>> + };
>> diff --git a/Documentation/devicetree/bindings/clock/mediatek,mt8196-sys-clock.yaml b/Documentation/devicetree/bindings/clock/mediatek,mt8196-sys-clock.yaml
>> new file mode 100644
>> index 000000000000..363ebe87c525
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/clock/mediatek,mt8196-sys-clock.yaml
>> @@ -0,0 +1,76 @@
>> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
>> +%YAML 1.2
>> +---
>> +$id: http://devicetree.org/schemas/clock/mediatek,mt8196-sys-clock.yaml#
>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
>> +
>> +title: MediaTek System Clock Controller for MT8196
>> +
>> +maintainers:
>> + - Guangjie Song <guangjie.song@...iatek.com>
>> + - Laura Nao <laura.nao@...labora.com>
>> +
>> +description: |
>> + The clock architecture in MediaTek SoCs is structured like below:
>> + PLLs -->
>> + dividers -->
>> + muxes
>> + -->
>> + clock gate
>> +
>> + The apmixedsys, apmixedsys_gp2, vlpckgen, armpll, ccipll, mfgpll and ptppll
>> + provide most of the PLLs which are generated from the SoC's 26MHZ crystal oscillator.
>> + The topckgen, topckgen_gp2 and vlpckgen provide dividers and muxes which
>> + provide the clock source to other IP blocks.
>> +
>> +properties:
>> + compatible:
>> + items:
>> + - enum:
>> + - mediatek,mt8196-apmixedsys
>> + - mediatek,mt8196-armpll-b-pll-ctrl
>> + - mediatek,mt8196-armpll-bl-pll-ctrl
>> + - mediatek,mt8196-armpll-ll-pll-ctrl
>> + - mediatek,mt8196-apmixedsys-gp2
>> + - mediatek,mt8196-ccipll-pll-ctrl
>> + - mediatek,mt8196-mfgpll-pll-ctrl
>> + - mediatek,mt8196-mfgpll-sc0-pll-ctrl
>> + - mediatek,mt8196-mfgpll-sc1-pll-ctrl
>> + - mediatek,mt8196-ptppll-pll-ctrl
>> + - mediatek,mt8196-topckgen
>> + - mediatek,mt8196-topckgen-gp2
>> + - mediatek,mt8196-vlpckgen
>> + - const: syscon
>
> Why everything is syscon?
Like all other MediaTek SoCs - each sub-IP has its own clock controller, and all
of those sub-IPs have part of the system controller.
It's just a MediaTek SoC being a... MediaTek SoC.
>
>> +
>> + reg:
>> + maxItems: 1
>> +
>> + '#clock-cells':
>> + const: 1
>> +
>> + mediatek,hardware-voter:
>> + $ref: /schemas/types.yaml#/definitions/phandle
>> + description: A phandle of the hw voter node
>
> Do not copy property name to description, but say something useful - for
> what? And why this cannot be or is not a proper interconnect?
>
Laura, please check the commit description of my power domains HWV patches
here: 20250623120154.109429-8-angelogioacchino.delregno@...labora.com
...and follow what krzk just said which... well, my bad for not complaining
about this during internal reviewing.
>> +
>> +required:
>> + - compatible
>> + - reg
>> + - '#clock-cells'
>> +
>> +additionalProperties: false
>> +
>> +examples:
>> + - |
>> + apmixedsys_clk: syscon@...00800 {
>> + compatible = "mediatek,mt8196-apmixedsys", "syscon";
>> + reg = <0x10000800 0x1000>;
>> + #clock-cells = <1>;
>> + };
>> + - |
>> + topckgen: syscon@...00000 {
>> + compatible = "mediatek,mt8196-topckgen", "syscon";
>> + reg = <0x10000000 0x800>;
>> + mediatek,hardware-voter = <&scp_hwv>;
>> + #clock-cells = <1>;
>> + };
>> +
>
>
>
>> +#define CLK_OVL1_DLO9 56
>> +#define CLK_OVL1_DLO10 57
>> +#define CLK_OVL1_DLO11 58
>> +#define CLK_OVL1_DLO12 59
>> +#define CLK_OVL1_OVLSYS_RELAY0 60
>> +#define CLK_OVL1_OVL_INLINEROT0 61
>> +#define CLK_OVL1_SMI 62
>> +
>> +
>> +/* VDEC_SOC_GCON_BASE */
>> +#define CLK_VDE1_LARB1_CKEN 0
>> +#define CLK_VDE1_LAT_CKEN 3
>
> IDs increment by 1, not 3.
Thank you, Krzysztof - sharp as always!
Cheers,
Angelo
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