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Message-ID: <20250624-wip-mca-updates-v4-0-236dd74f645f@amd.com>
Date: Tue, 24 Jun 2025 14:15:55 +0000
From: Yazen Ghannam <yazen.ghannam@....com>
To: <x86@...nel.org>, Tony Luck <tony.luck@...el.com>, "Rafael J. Wysocki"
<rafael@...nel.org>, Len Brown <lenb@...nel.org>
CC: <linux-kernel@...r.kernel.org>, <linux-edac@...r.kernel.org>,
<Smita.KoralahalliChannabasappa@....com>, Qiuxu Zhuo <qiuxu.zhuo@...el.com>,
<linux-acpi@...r.kernel.org>, Yazen Ghannam <yazen.ghannam@....com>
Subject: [PATCH v4 00/22] AMD MCA interrupts rework
Hi all,
This set unifies the AMD MCA interrupt handlers with common MCA code.
The goal is to avoid duplicating functionality like reading and clearing
MCA banks.
Based on feedback, this revision also include changes to the MCA init
flow.
Patches 1-8:
General fixes and cleanups.
Patches 9-14:
Add BSP-only init flow and related changes.
Patches 15-18:
Updates from v1 set.
Patches 19-21:
Interrupt storm handling rebased on current set.
Patch 22:
Add support to get threshold limit from APEI HEST.
Thanks,
Yazen
---
Changes in v4:
- Rebase on v6.16-rc3.
- Address comments from Boris about function names.
- Redo DFR handler integration.
- Drop AMD APIC LVT rework.
- Include more AMD thresholding reworks and fixes.
- Add support to get threshold limit from APEI HEST.
- Reorder patches so most fixes and reworks are at the beginning.
- Link to v3: https://lore.kernel.org/r/20250415-wip-mca-updates-v3-0-8ffd9eb4aa56@amd.com
Changes in v3:
- Rebased on tip/x86/merge rather than tip/master.
- Updated MSR access helpers (*msrl -> *msrq).
- Add patch to fix polling after a storm.
- Link to v2: https://lore.kernel.org/r/20250213-wip-mca-updates-v2-0-3636547fe05f@amd.com
Changes in v2:
- Add general cleanup pre-patches.
- Add changes for BSP-only init.
- Add interrupt storm handling for AMD.
- Link to v1: https://lore.kernel.org/r/20240523155641.2805411-1-yazen.ghannam@amd.com
---
Borislav Petkov (1):
x86/mce: Cleanup bank processing on init
Smita Koralahalli (1):
x86/mce: Handle AMD threshold interrupt storms
Yazen Ghannam (20):
x86/mce: Don't remove sysfs if thresholding sysfs init fails
x86/mce: Restore poll settings after storm subsides
x86/mce/amd: Add default names for MCA banks and blocks
x86/mce/amd: Fix threshold limit reset
x86/mce/amd: Rename threshold restart function
x86/mce/amd: Remove return value for mce_threshold_{create,remove}_device()
x86/mce/amd: Remove smca_banks_map
x86/mce/amd: Put list_head in threshold_bank
x86/mce: Remove __mcheck_cpu_init_early()
x86/mce: Define BSP-only init
x86/mce: Define BSP-only SMCA init
x86/mce: Do 'UNKNOWN' vendor check early
x86/mce: Separate global and per-CPU quirks
x86/mce: Move machine_check_poll() status checks to helper functions
x86/mce: Unify AMD THR handler with MCA Polling
x86/mce: Unify AMD DFR handler with MCA Polling
x86/mce/amd: Support SMCA Corrected Error Interrupt
x86/mce/amd: Remove redundant reset_block()
x86/mce/amd: Define threshold restart function for banks
x86/mce: Save and use APEI corrected threshold limit
arch/x86/include/asm/mce.h | 23 ++-
arch/x86/kernel/acpi/apei.c | 2 +
arch/x86/kernel/cpu/common.c | 1 +
arch/x86/kernel/cpu/mce/amd.c | 366 ++++++++++++++----------------------
arch/x86/kernel/cpu/mce/core.c | 363 +++++++++++++++++------------------
arch/x86/kernel/cpu/mce/intel.c | 18 ++
arch/x86/kernel/cpu/mce/internal.h | 12 ++
arch/x86/kernel/cpu/mce/threshold.c | 16 ++
8 files changed, 379 insertions(+), 422 deletions(-)
---
base-commit: 86731a2a651e58953fc949573895f2fa6d456841
change-id: 20250210-wip-mca-updates-bed2a67c9c57
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