linux-kernel - Re: [PATCHv2 0/3] x86: Make 5-level paging support unconditional for x86-64

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Message-ID: <3EB75889-2194-402F-AF85-2CC96DA5D8F2@zytor.com>
Date: Tue, 24 Jun 2025 01:22:00 -0700
From: "H. Peter Anvin" <hpa@...or.com>
To: Khalid Ali <khaliidcaliy@...il.com>, tglx@...utronix.de, mingo@...hat.com,
        bp@...en8.de, dave.hansen@...ux.intel.com, corbet@....net
CC: luto@...nel.org, peterz@...radead.org, ardb@...nel.org,
        jan.kiszka@...mens.com, kbingham@...nel.org,
        kirill.shutemov@...ux.intel.com, michael.roth@....com,
        rick.p.edgecombe@...el.com, brijesh.singh@....com,
        sandipan.das@....com, jgross@...e.com, thomas.lendacky@....com,
        linux-kernel@...r.kernel.org, linux-doc@...r.kernel.org,
        linux-efi@...r.kernel.org, linux-mm@...ck.org
Subject: Re: [PATCHv2 0/3] x86: Make 5-level paging support unconditional for x86-64

On June 24, 2025 1:11:15 AM PDT, Khalid Ali <khaliidcaliy@...il.com> wrote:
>>Both Intel and AMD CPUs support 5-level paging, which is expected to
>>become more widely adopted in the future.
>>
>>Remove CONFIG_X86_5LEVEL.
>>
>>In preparation to that remove CONFIG_DYNAMIC_MEMORY_LAYOUT and make
>>SPARSEMEM_VMEMMAP the only memory model.
>>
>>v2:
>> - Fix 32-bit build by wrapping p4d_set_huge() and p4d_clear_huge() in
>>   #if CONFIG_PGTABLE_LEVELS > 4;
>> - Rebased onto current tip/master;
>>
>>Kirill A. Shutemov (3):
>>  x86/64/mm: Always use dynamic memory layout
>>  x86/64/mm: Make SPARSEMEM_VMEMMAP the only memory model
>>  x86/64/mm: Make 5-level paging support unconditional
>>
>> Documentation/arch/x86/cpuinfo.rst            |  8 ++---
>> .../arch/x86/x86_64/5level-paging.rst         |  9 ------
>> arch/x86/Kconfig                              | 32 ++-----------------
>> arch/x86/Kconfig.cpufeatures                  |  4 ---
>> arch/x86/boot/compressed/pgtable_64.c         | 11 ++-----
>> arch/x86/boot/header.S                        |  4 ---
>> arch/x86/boot/startup/map_kernel.c            |  5 +--
>> arch/x86/include/asm/page_64.h                |  2 --
>> arch/x86/include/asm/page_64_types.h          | 11 -------
>> arch/x86/include/asm/pgtable_64_types.h       | 24 --------------
>> arch/x86/kernel/alternative.c                 |  2 +-
>> arch/x86/kernel/head64.c                      |  4 ---
>> arch/x86/kernel/head_64.S                     |  2 --
>> arch/x86/mm/init.c                            |  4 ---
>> arch/x86/mm/init_64.c                         |  9 +-----
>> arch/x86/mm/pgtable.c                         |  2 +-
>> drivers/firmware/efi/libstub/x86-5lvl.c       |  2 +-
>> scripts/gdb/linux/pgtable.py                  |  4 +--
>> 18 files changed, 13 insertions(+), 126 deletions(-)
>
>I think i am too late, however this is completely wrong. There are still processors that doesn't support
>5-level paging which is mordern. We may call those processors old, however they are still common and used.
>
>So this patch seem too early for that. Some intel core-i5 and core-i7 doesn't support 5-level paging at all.
>
>This will break x86_64 cpus that doesn't support 5-level paging.

Uh, no. Kernels compiled with 5-level support also support 4 levels.