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Message-ID: <m3i4z5ell2lhtpverw5slnxidd32lmtqcdpwcljtr5betki6s5@kiq2bibj5lt2>
Date: Tue, 24 Jun 2025 11:49:45 +0300
From: "Kirill A. Shutemov" <kirill.shutemov@...ux.intel.com>
To: Khalid Ali <khaliidcaliy@...il.com>
Cc: tglx@...utronix.de, mingo@...hat.com, bp@...en8.de,
dave.hansen@...ux.intel.com, hpa@...or.com, corbet@....net, luto@...nel.org,
peterz@...radead.org, ardb@...nel.org, jan.kiszka@...mens.com, kbingham@...nel.org,
michael.roth@....com, rick.p.edgecombe@...el.com, brijesh.singh@....com,
sandipan.das@....com, jgross@...e.com, thomas.lendacky@....com,
linux-kernel@...r.kernel.org, linux-doc@...r.kernel.org, linux-efi@...r.kernel.org,
linux-mm@...ck.org
Subject: Re: [PATCHv2 0/3] x86: Make 5-level paging support unconditional for
x86-64
On Tue, Jun 24, 2025 at 08:11:15AM +0000, Khalid Ali wrote:
> This will break x86_64 cpus that doesn't support 5-level paging.
No, it won't.
The patchset removes compile-time config option to disable 5-level paging.
After tha patchset all kernels will be built with 5-level paging *support*.
The actual paging mode is chosen at boot time based on machine
capabilities and kernel command line. Older HW will boot in 4-level paging
mode just fine.
--
Kiryl Shutsemau / Kirill A. Shutemov
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