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Message-ID: <20250625141705.151383-2-prabhakar.mahadev-lad.rj@bp.renesas.com>
Date: Wed, 25 Jun 2025 15:17:03 +0100
From: Prabhakar <prabhakar.csengg@...il.com>
To: Geert Uytterhoeven <geert+renesas@...der.be>,
Michael Turquette <mturquette@...libre.com>,
Stephen Boyd <sboyd@...nel.org>,
Rob Herring <robh@...nel.org>,
Krzysztof Kozlowski <krzk+dt@...nel.org>,
Conor Dooley <conor+dt@...nel.org>,
Magnus Damm <magnus.damm@...il.com>
Cc: linux-renesas-soc@...r.kernel.org,
linux-clk@...r.kernel.org,
linux-kernel@...r.kernel.org,
devicetree@...r.kernel.org,
Prabhakar <prabhakar.csengg@...il.com>,
Biju Das <biju.das.jz@...renesas.com>,
Fabrizio Castro <fabrizio.castro.jz@...esas.com>,
Lad Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com>
Subject: [PATCH 1/3] dt-bindings: clock: renesas,r9a09g077/87: Add SDHI_CLKHS clock ID
From: Lad Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com>
Add the SDHI high-speed clock (SDHI_CLKHS) definition for the Renesas
RZ/T2H (R9A09G077) and RZ/N2H (R9A09G087) SoCs. SDHI_CLKHS is used as
a core clock for the SDHI IP and operates at 800MHz.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com>
---
include/dt-bindings/clock/renesas,r9a09g077-cpg-mssr.h | 1 +
include/dt-bindings/clock/renesas,r9a09g087-cpg-mssr.h | 1 +
2 files changed, 2 insertions(+)
diff --git a/include/dt-bindings/clock/renesas,r9a09g077-cpg-mssr.h b/include/dt-bindings/clock/renesas,r9a09g077-cpg-mssr.h
index f6e5f62b07c4..7ecc4f0b235a 100644
--- a/include/dt-bindings/clock/renesas,r9a09g077-cpg-mssr.h
+++ b/include/dt-bindings/clock/renesas,r9a09g077-cpg-mssr.h
@@ -24,5 +24,6 @@
#define R9A09G077_CLK_PCLKH 12
#define R9A09G077_CLK_PCLKM 13
#define R9A09G077_CLK_PCLKL 14
+#define R9A09G077_SDHI_CLKHS 15
#endif /* __DT_BINDINGS_CLOCK_RENESAS_R9A09G077_CPG_H__ */
diff --git a/include/dt-bindings/clock/renesas,r9a09g087-cpg-mssr.h b/include/dt-bindings/clock/renesas,r9a09g087-cpg-mssr.h
index f28166d6015f..925e57703925 100644
--- a/include/dt-bindings/clock/renesas,r9a09g087-cpg-mssr.h
+++ b/include/dt-bindings/clock/renesas,r9a09g087-cpg-mssr.h
@@ -24,5 +24,6 @@
#define R9A09G087_CLK_PCLKH 12
#define R9A09G087_CLK_PCLKM 13
#define R9A09G087_CLK_PCLKL 14
+#define R9A09G087_SDHI_CLKHS 15
#endif /* __DT_BINDINGS_CLOCK_RENESAS_R9A09G087_CPG_H__ */
--
2.49.0
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