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Message-ID: <20250625210456.GA2177479-robh@kernel.org>
Date: Wed, 25 Jun 2025 16:04:56 -0500
From: Rob Herring <robh@...nel.org>
To: Jacky Chou <jacky_chou@...eedtech.com>
Cc: bhelgaas@...gle.com, lpieralisi@...nel.org, kwilczynski@...nel.org,
mani@...nel.org, krzk+dt@...nel.org, conor+dt@...nel.org,
joel@....id.au, andrew@...econstruct.com.au, vkoul@...nel.org,
kishon@...nel.org, linus.walleij@...aro.org, p.zabel@...gutronix.de,
linux-aspeed@...ts.ozlabs.org, linux-pci@...r.kernel.org,
devicetree@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
linux-kernel@...r.kernel.org, linux-phy@...ts.infradead.org,
openbmc@...ts.ozlabs.org, linux-gpio@...r.kernel.org,
elbadrym@...gle.com, romlem@...gle.com, anhphan@...gle.com,
wak@...gle.com, yuxiaozhang@...gle.com, BMC-SW@...eedtech.com
Subject: Re: [PATCH 3/7] dt-bindings: pci: Add document for ASPEED PCIe RC
On Fri, Jun 13, 2025 at 11:29:57AM +0800, Jacky Chou wrote:
> Add device tree binding documentation for the ASPEED PCIe Root Complex
> controller. This binding describes the required and optional properties
> for configuring the PCIe RC node, including support for syscon phandles,
> MSI, clocks, resets, and interrupt mapping. The schema enforces strict
> property validation and provides a comprehensive example for reference.
>
> Signed-off-by: Jacky Chou <jacky_chou@...eedtech.com>
> ---
> .../devicetree/bindings/pci/aspeed-pcie.yaml | 159 ++++++++++++++++++
> 1 file changed, 159 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/pci/aspeed-pcie.yaml
>
> diff --git a/Documentation/devicetree/bindings/pci/aspeed-pcie.yaml b/Documentation/devicetree/bindings/pci/aspeed-pcie.yaml
> new file mode 100644
> index 000000000000..5b50a9e2d472
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/pci/aspeed-pcie.yaml
> @@ -0,0 +1,159 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/pci/aspeed-pcie.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: ASPEED PCIe Root Complex Controller
> +
> +maintainers:
> + - Jacky Chou <jacky_chou@...eedtech.com>
> +
> +description: |
> + Device tree binding for the ASPEED PCIe Root Complex controller.
> +
> +properties:
> + compatible:
> + enum:
> + - aspeed,ast2600-pcie
> + - aspeed,ast2700-pcie
> +
> + device_type:
> + const: pci
> +
> + reg:
> + maxItems: 1
> +
> + ranges:
> + minItems: 2
> + maxItems: 2
> +
> + interrupts:
> + description: IntX and MSI interrupt
> +
> + resets:
> + items:
> + - description: Module reset
> + - description: PCIe PERST
> +
> + reset-names:
> + items:
> + - const: h2x
> + - const: perst
> +
> + msi-parent: true
> +
> + msi_address:
> + $ref: /schemas/types.yaml#/definitions/uint32
> + description: MSI address
What's this for?
> +
> + aspeed,ahbc:
> + $ref: /schemas/types.yaml#/definitions/phandle
> + description: Phandle to ASPEED AHBC syscon.
> +
> + aspeed,pciecfg:
> + $ref: /schemas/types.yaml#/definitions/phandle
> + description: Phandle to ASPEED PCIe configuration syscon.
> +
> + aspeed,pciephy:
> + $ref: /schemas/types.yaml#/definitions/phandle
> + description: Phandle to ASPEED PCIe PHY syscon.
Use the phy binding and make the phy control a separate driver.
Rob
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