linux-kernel - Re: [PATCH v3 0/4] Add CMN PLL clock controller support for IPQ5424

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Message-ID: <1ba89074-9614-4f64-ba8b-ca81abc9a24c@quicinc.com>
Date: Wed, 25 Jun 2025 15:05:32 +0800
From: Luo Jie <quic_luoj@...cinc.com>
To: Bjorn Andersson <andersson@...nel.org>,
        Michael Turquette
	<mturquette@...libre.com>,
        Stephen Boyd <sboyd@...nel.org>, Rob Herring
	<robh@...nel.org>,
        Krzysztof Kozlowski <krzk+dt@...nel.org>,
        Conor Dooley
	<conor+dt@...nel.org>,
        Konrad Dybcio <konradybcio@...nel.org>
CC: <linux-arm-msm@...r.kernel.org>, <linux-clk@...r.kernel.org>,
        <devicetree@...r.kernel.org>, <linux-kernel@...r.kernel.org>,
        <quic_kkumarcs@...cinc.com>, <quic_suruchia@...cinc.com>,
        <quic_pavir@...cinc.com>, <quic_linchen@...cinc.com>,
        <quic_leiwei@...cinc.com>,
        Konrad Dybcio <konrad.dybcio@....qualcomm.com>
Subject: Re: [PATCH v3 0/4] Add CMN PLL clock controller support for IPQ5424

Hi Bjorn,

I wanted to check on this patch series. All review comments
have been addressed, and there have been no further objections.
Would you consider merging these patches? Thank you for your
time and feedback!

Best Regards,
Jie

On 6/10/2025 6:35 PM, Luo Jie wrote:
> The CMN PLL block of IPQ5424 is almost same as that of IPQ9574
> which is currently supported by the driver. The only difference
> is that the fixed output clocks to NSS and PPE from CMN PLL have
> a different clock rate. In IPQ5424, the output clocks are supplied
> to NSS at 300 MHZ and to PPE at 375 MHZ.
> 
> This patch series extends the CMN PLL driver to support IPQ5424.
> It also adds the SoC specific header file to export the CMN PLL
> output clock specifiers for IPQ5424. The new table of output
> clocks is added for the CMN PLL of IPQ5424, which is acquired
> from the device according to the compatible.
> 
> Signed-off-by: Luo Jie <quic_luoj@...cinc.com>
> ---
> Changes in v3:
> - Collect review tags for the DT binding and driver patches.
> - Rebase onto the latest code to resolve conflicts in the DTS patch.
> - Link to v2: https://lore.kernel.org/r/20250411-qcom_ipq5424_cmnpll-v2-0-7252c192e078@quicinc.com
> 
> Changes in v2:
> - Alphanumeric order for the compatible strings in dtbindings.
> - Add the IPQ5424 SoC specific header file to export the clock specifiers.
> - Drop the comma of the sentinel entry of the output clock array.
> - Add Reviewed-by tag on the DTS patches.
> - Link to v1: https://lore.kernel.org/r/20250321-qcom_ipq5424_cmnpll-v1-0-3ea8e5262da4@quicinc.com
> 
> ---
> Luo Jie (4):
>        dt-bindings: clock: qcom: Add CMN PLL support for IPQ5424 SoC
>        clk: qcom: cmnpll: Add IPQ5424 SoC support
>        arm64: dts: ipq5424: Add CMN PLL node
>        arm64: dts: qcom: Update IPQ5424 xo_board to use fixed factor clock
> 
>   .../bindings/clock/qcom,ipq9574-cmn-pll.yaml       |  1 +
>   arch/arm64/boot/dts/qcom/ipq5424-rdp466.dts        | 24 +++++++++++++--
>   arch/arm64/boot/dts/qcom/ipq5424.dtsi              | 27 ++++++++++++++++-
>   drivers/clk/qcom/ipq-cmn-pll.c                     | 35 ++++++++++++++++++----
>   include/dt-bindings/clock/qcom,ipq5424-cmn-pll.h   | 22 ++++++++++++++
>   5 files changed, 101 insertions(+), 8 deletions(-)
> ---
> base-commit: b27cc623e01be9de1580eaa913508b237a7a9673
> change-id: 20250610-qcom_ipq5424_cmnpll-22b232bb18fd
> 
> Best regards,