[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-Id: <20250626195610.405379-9-kan.liang@linux.intel.com>
Date: Thu, 26 Jun 2025 12:56:05 -0700
From: kan.liang@...ux.intel.com
To: peterz@...radead.org,
mingo@...hat.com,
acme@...nel.org,
namhyung@...nel.org,
tglx@...utronix.de,
dave.hansen@...ux.intel.com,
irogers@...gle.com,
adrian.hunter@...el.com,
jolsa@...nel.org,
alexander.shishkin@...ux.intel.com,
linux-kernel@...r.kernel.org
Cc: dapeng1.mi@...ux.intel.com,
ak@...ux.intel.com,
zide.chen@...el.com,
mark.rutland@....com,
broonie@...nel.org,
ravi.bangoria@....com,
Kan Liang <kan.liang@...ux.intel.com>
Subject: [RFC PATCH V2 08/13] perf/x86: Add YMM into sample_simd_vec_regs
From: Kan Liang <kan.liang@...ux.intel.com>
The YMM0-15 is composed of XMM and YMMH. It requires 2 XSAVE commands to
get the complete value. Internally, the XMM and YMMH are stored in
different structures, which follow the XSAVE format. But the output
dumps the YMM as a whole.
The qwords 4 imply YMM.
Signed-off-by: Kan Liang <kan.liang@...ux.intel.com>
---
arch/x86/events/core.c | 15 +++++++++++++++
arch/x86/events/perf_event.h | 1 +
arch/x86/include/asm/perf_event.h | 4 ++++
arch/x86/include/uapi/asm/perf_regs.h | 4 +++-
arch/x86/kernel/perf_regs.c | 7 ++++++-
5 files changed, 29 insertions(+), 2 deletions(-)
diff --git a/arch/x86/events/core.c b/arch/x86/events/core.c
index 2515179ac664..20c825e83a3f 100644
--- a/arch/x86/events/core.c
+++ b/arch/x86/events/core.c
@@ -420,6 +420,9 @@ static void x86_pmu_get_ext_regs(struct x86_perf_regs *perf_regs, u64 mask)
if (mask & XFEATURE_MASK_SSE &&
xsave->header.xfeatures & BIT_ULL(XFEATURE_SSE))
perf_regs->xmm_space = xsave->i387.xmm_space;
+
+ if (mask & XFEATURE_MASK_YMM)
+ perf_regs->ymmh = get_xsave_addr(xsave, XFEATURE_YMM);
}
static void release_ext_regs_buffers(void)
@@ -446,6 +449,8 @@ static void reserve_ext_regs_buffers(void)
if (x86_pmu.ext_regs_mask & X86_EXT_REGS_XMM)
mask |= XFEATURE_MASK_SSE;
+ if (x86_pmu.ext_regs_mask & X86_EXT_REGS_YMM)
+ mask |= XFEATURE_MASK_YMM;
size = xstate_calculate_size(mask, true);
@@ -726,6 +731,9 @@ int x86_pmu_hw_config(struct perf_event *event)
if (event->attr.sample_simd_vec_reg_qwords >= PERF_X86_XMM_QWORDS &&
!(x86_pmu.ext_regs_mask & X86_EXT_REGS_XMM))
return -EINVAL;
+ if (event->attr.sample_simd_vec_reg_qwords >= PERF_X86_YMM_QWORDS &&
+ !(x86_pmu.ext_regs_mask & X86_EXT_REGS_YMM))
+ return -EINVAL;
}
}
return x86_setup_perfctr(event);
@@ -1838,6 +1846,13 @@ void x86_pmu_setup_regs_data(struct perf_event *event,
mask |= XFEATURE_MASK_SSE;
}
+ if (attr->sample_simd_regs_enabled) {
+ if (attr->sample_simd_vec_reg_qwords >= PERF_X86_YMM_QWORDS) {
+ perf_regs->ymmh_regs = NULL;
+ mask |= XFEATURE_MASK_YMM;
+ }
+ }
+
mask &= ~ignore_mask;
if (mask)
x86_pmu_get_ext_regs(perf_regs, mask);
diff --git a/arch/x86/events/perf_event.h b/arch/x86/events/perf_event.h
index 69964433a245..7d332d0247ed 100644
--- a/arch/x86/events/perf_event.h
+++ b/arch/x86/events/perf_event.h
@@ -701,6 +701,7 @@ enum {
enum {
X86_EXT_REGS_XMM = BIT_ULL(0),
+ X86_EXT_REGS_YMM = BIT_ULL(1),
};
#define PERF_PEBS_DATA_SOURCE_MAX 0x100
diff --git a/arch/x86/include/asm/perf_event.h b/arch/x86/include/asm/perf_event.h
index 538219c59979..81e3143fd91a 100644
--- a/arch/x86/include/asm/perf_event.h
+++ b/arch/x86/include/asm/perf_event.h
@@ -597,6 +597,10 @@ struct x86_perf_regs {
u64 *xmm_regs;
u32 *xmm_space; /* for xsaves */
};
+ union {
+ u64 *ymmh_regs;
+ struct ymmh_struct *ymmh;
+ };
};
extern unsigned long perf_arch_instruction_pointer(struct pt_regs *regs);
diff --git a/arch/x86/include/uapi/asm/perf_regs.h b/arch/x86/include/uapi/asm/perf_regs.h
index bd8af802f757..feb3e8f80761 100644
--- a/arch/x86/include/uapi/asm/perf_regs.h
+++ b/arch/x86/include/uapi/asm/perf_regs.h
@@ -59,6 +59,8 @@ enum perf_event_x86_regs {
#define PERF_X86_SIMD_VEC_MASK GENMASK_ULL(PERF_X86_SIMD_VEC_REGS_MAX - 1, 0)
#define PERF_X86_XMM_QWORDS 2
-#define PERF_X86_SIMD_QWORDS_MAX PERF_X86_XMM_QWORDS
+#define PERF_X86_YMM_QWORDS 4
+#define PERF_X86_YMMH_QWORDS (PERF_X86_YMM_QWORDS / 2)
+#define PERF_X86_SIMD_QWORDS_MAX PERF_X86_YMM_QWORDS
#endif /* _ASM_X86_PERF_REGS_H */
diff --git a/arch/x86/kernel/perf_regs.c b/arch/x86/kernel/perf_regs.c
index 638b9e186c50..37cf0a282915 100644
--- a/arch/x86/kernel/perf_regs.c
+++ b/arch/x86/kernel/perf_regs.c
@@ -93,6 +93,10 @@ u64 perf_simd_reg_value(struct pt_regs *regs, int idx,
if (!perf_regs->xmm_regs)
return 0;
return perf_regs->xmm_regs[idx * PERF_X86_XMM_QWORDS + qwords_idx];
+ } else if (qwords_idx < PERF_X86_YMM_QWORDS) {
+ if (!perf_regs->ymmh_regs)
+ return 0;
+ return perf_regs->ymmh_regs[idx * PERF_X86_YMMH_QWORDS + qwords_idx - PERF_X86_XMM_QWORDS];
}
return 0;
@@ -109,7 +113,8 @@ int perf_simd_reg_validate(u16 vec_qwords, u64 vec_mask,
if (vec_mask)
return -EINVAL;
} else {
- if (vec_qwords != PERF_X86_XMM_QWORDS)
+ if (vec_qwords != PERF_X86_XMM_QWORDS &&
+ vec_qwords != PERF_X86_YMM_QWORDS)
return -EINVAL;
if (vec_mask & ~PERF_X86_SIMD_VEC_MASK)
return -EINVAL;
--
2.38.1
Powered by blists - more mailing lists