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Message-Id: <20250626195610.405379-10-kan.liang@linux.intel.com>
Date: Thu, 26 Jun 2025 12:56:06 -0700
From: kan.liang@...ux.intel.com
To: peterz@...radead.org,
mingo@...hat.com,
acme@...nel.org,
namhyung@...nel.org,
tglx@...utronix.de,
dave.hansen@...ux.intel.com,
irogers@...gle.com,
adrian.hunter@...el.com,
jolsa@...nel.org,
alexander.shishkin@...ux.intel.com,
linux-kernel@...r.kernel.org
Cc: dapeng1.mi@...ux.intel.com,
ak@...ux.intel.com,
zide.chen@...el.com,
mark.rutland@....com,
broonie@...nel.org,
ravi.bangoria@....com,
Kan Liang <kan.liang@...ux.intel.com>
Subject: [RFC PATCH V2 09/13] perf/x86: Add ZMM into sample_simd_vec_regs
From: Kan Liang <kan.liang@...ux.intel.com>
The ZMM0-15 is composed of XMM, YMMH, and ZMMH. It requires 3 XSAVE
commands to get the complete value.
The ZMM16-31/YMM16-31/XMM16-31 are also supported, which only require
the XSAVE Hi16_ZMM.
Internally, the XMM, YMMH, ZMMH and Hi16_ZMM are stored in different
structures, which follow the XSAVE format. But the output dumps the ZMM
or Hi16 XMM/YMM/ZMM as a whole.
The qwords 8 imply ZMM.
Signed-off-by: Kan Liang <kan.liang@...ux.intel.com>
---
arch/x86/events/core.c | 24 ++++++++++++++++++++++++
arch/x86/events/perf_event.h | 2 ++
arch/x86/include/asm/perf_event.h | 8 ++++++++
arch/x86/include/uapi/asm/perf_regs.h | 8 ++++++--
arch/x86/kernel/perf_regs.c | 13 ++++++++++++-
5 files changed, 52 insertions(+), 3 deletions(-)
diff --git a/arch/x86/events/core.c b/arch/x86/events/core.c
index 20c825e83a3f..3c05ca98ec3f 100644
--- a/arch/x86/events/core.c
+++ b/arch/x86/events/core.c
@@ -423,6 +423,10 @@ static void x86_pmu_get_ext_regs(struct x86_perf_regs *perf_regs, u64 mask)
if (mask & XFEATURE_MASK_YMM)
perf_regs->ymmh = get_xsave_addr(xsave, XFEATURE_YMM);
+ if (mask & XFEATURE_MASK_ZMM_Hi256)
+ perf_regs->zmmh = get_xsave_addr(xsave, XFEATURE_ZMM_Hi256);
+ if (mask & XFEATURE_MASK_Hi16_ZMM)
+ perf_regs->h16zmm = get_xsave_addr(xsave, XFEATURE_Hi16_ZMM);
}
static void release_ext_regs_buffers(void)
@@ -451,6 +455,10 @@ static void reserve_ext_regs_buffers(void)
mask |= XFEATURE_MASK_SSE;
if (x86_pmu.ext_regs_mask & X86_EXT_REGS_YMM)
mask |= XFEATURE_MASK_YMM;
+ if (x86_pmu.ext_regs_mask & X86_EXT_REGS_ZMMH)
+ mask |= XFEATURE_MASK_ZMM_Hi256;
+ if (x86_pmu.ext_regs_mask & X86_EXT_REGS_H16ZMM)
+ mask |= XFEATURE_MASK_Hi16_ZMM;
size = xstate_calculate_size(mask, true);
@@ -734,6 +742,13 @@ int x86_pmu_hw_config(struct perf_event *event)
if (event->attr.sample_simd_vec_reg_qwords >= PERF_X86_YMM_QWORDS &&
!(x86_pmu.ext_regs_mask & X86_EXT_REGS_YMM))
return -EINVAL;
+ if (event->attr.sample_simd_vec_reg_qwords >= PERF_X86_ZMM_QWORDS &&
+ !(x86_pmu.ext_regs_mask & X86_EXT_REGS_ZMMH))
+ return -EINVAL;
+ if ((fls64(event->attr.sample_simd_vec_reg_intr) > PERF_X86_H16ZMM_BASE ||
+ fls64(event->attr.sample_simd_vec_reg_user) > PERF_X86_H16ZMM_BASE) &&
+ !(x86_pmu.ext_regs_mask & X86_EXT_REGS_H16ZMM))
+ return -EINVAL;
}
}
return x86_setup_perfctr(event);
@@ -1851,6 +1866,15 @@ void x86_pmu_setup_regs_data(struct perf_event *event,
perf_regs->ymmh_regs = NULL;
mask |= XFEATURE_MASK_YMM;
}
+ if (attr->sample_simd_vec_reg_qwords >= PERF_X86_ZMM_QWORDS) {
+ perf_regs->zmmh_regs = NULL;
+ mask |= XFEATURE_MASK_ZMM_Hi256;
+ }
+ if (fls64(attr->sample_simd_vec_reg_intr) > PERF_X86_H16ZMM_BASE ||
+ fls64(attr->sample_simd_vec_reg_user) > PERF_X86_H16ZMM_BASE) {
+ perf_regs->h16zmm_regs = NULL;
+ mask |= XFEATURE_MASK_Hi16_ZMM;
+ }
}
mask &= ~ignore_mask;
diff --git a/arch/x86/events/perf_event.h b/arch/x86/events/perf_event.h
index 7d332d0247ed..cc42e9d3e13d 100644
--- a/arch/x86/events/perf_event.h
+++ b/arch/x86/events/perf_event.h
@@ -702,6 +702,8 @@ enum {
enum {
X86_EXT_REGS_XMM = BIT_ULL(0),
X86_EXT_REGS_YMM = BIT_ULL(1),
+ X86_EXT_REGS_ZMMH = BIT_ULL(2),
+ X86_EXT_REGS_H16ZMM = BIT_ULL(3),
};
#define PERF_PEBS_DATA_SOURCE_MAX 0x100
diff --git a/arch/x86/include/asm/perf_event.h b/arch/x86/include/asm/perf_event.h
index 81e3143fd91a..2d78bd9649bd 100644
--- a/arch/x86/include/asm/perf_event.h
+++ b/arch/x86/include/asm/perf_event.h
@@ -601,6 +601,14 @@ struct x86_perf_regs {
u64 *ymmh_regs;
struct ymmh_struct *ymmh;
};
+ union {
+ u64 *zmmh_regs;
+ struct avx_512_zmm_uppers_state *zmmh;
+ };
+ union {
+ u64 *h16zmm_regs;
+ struct avx_512_hi16_state *h16zmm;
+ };
};
extern unsigned long perf_arch_instruction_pointer(struct pt_regs *regs);
diff --git a/arch/x86/include/uapi/asm/perf_regs.h b/arch/x86/include/uapi/asm/perf_regs.h
index feb3e8f80761..f74e3ba65be2 100644
--- a/arch/x86/include/uapi/asm/perf_regs.h
+++ b/arch/x86/include/uapi/asm/perf_regs.h
@@ -55,12 +55,16 @@ enum perf_event_x86_regs {
#define PERF_REG_EXTENDED_MASK (~((1ULL << PERF_REG_X86_XMM0) - 1))
-#define PERF_X86_SIMD_VEC_REGS_MAX 16
+#define PERF_X86_SIMD_VEC_REGS_MAX 32
#define PERF_X86_SIMD_VEC_MASK GENMASK_ULL(PERF_X86_SIMD_VEC_REGS_MAX - 1, 0)
+#define PERF_X86_H16ZMM_BASE 16
+
#define PERF_X86_XMM_QWORDS 2
#define PERF_X86_YMM_QWORDS 4
#define PERF_X86_YMMH_QWORDS (PERF_X86_YMM_QWORDS / 2)
-#define PERF_X86_SIMD_QWORDS_MAX PERF_X86_YMM_QWORDS
+#define PERF_X86_ZMM_QWORDS 8
+#define PERF_X86_ZMMH_QWORDS (PERF_X86_ZMM_QWORDS / 2)
+#define PERF_X86_SIMD_QWORDS_MAX PERF_X86_ZMM_QWORDS
#endif /* _ASM_X86_PERF_REGS_H */
diff --git a/arch/x86/kernel/perf_regs.c b/arch/x86/kernel/perf_regs.c
index 37cf0a282915..74e05e2e5c90 100644
--- a/arch/x86/kernel/perf_regs.c
+++ b/arch/x86/kernel/perf_regs.c
@@ -89,6 +89,12 @@ u64 perf_simd_reg_value(struct pt_regs *regs, int idx,
qwords_idx >= PERF_X86_SIMD_QWORDS_MAX))
return 0;
+ if (idx >= PERF_X86_H16ZMM_BASE) {
+ if (!perf_regs->h16zmm_regs)
+ return 0;
+ return perf_regs->h16zmm_regs[idx * PERF_X86_ZMM_QWORDS + qwords_idx];
+ }
+
if (qwords_idx < PERF_X86_XMM_QWORDS) {
if (!perf_regs->xmm_regs)
return 0;
@@ -97,6 +103,10 @@ u64 perf_simd_reg_value(struct pt_regs *regs, int idx,
if (!perf_regs->ymmh_regs)
return 0;
return perf_regs->ymmh_regs[idx * PERF_X86_YMMH_QWORDS + qwords_idx - PERF_X86_XMM_QWORDS];
+ } else if (qwords_idx < PERF_X86_ZMM_QWORDS) {
+ if (!perf_regs->zmmh_regs)
+ return 0;
+ return perf_regs->zmmh_regs[idx * PERF_X86_ZMMH_QWORDS + qwords_idx - PERF_X86_YMM_QWORDS];
}
return 0;
@@ -114,7 +124,8 @@ int perf_simd_reg_validate(u16 vec_qwords, u64 vec_mask,
return -EINVAL;
} else {
if (vec_qwords != PERF_X86_XMM_QWORDS &&
- vec_qwords != PERF_X86_YMM_QWORDS)
+ vec_qwords != PERF_X86_YMM_QWORDS &&
+ vec_qwords != PERF_X86_ZMM_QWORDS)
return -EINVAL;
if (vec_mask & ~PERF_X86_SIMD_VEC_MASK)
return -EINVAL;
--
2.38.1
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