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Message-Id: <20250626195610.405379-11-kan.liang@linux.intel.com>
Date: Thu, 26 Jun 2025 12:56:07 -0700
From: kan.liang@...ux.intel.com
To: peterz@...radead.org,
mingo@...hat.com,
acme@...nel.org,
namhyung@...nel.org,
tglx@...utronix.de,
dave.hansen@...ux.intel.com,
irogers@...gle.com,
adrian.hunter@...el.com,
jolsa@...nel.org,
alexander.shishkin@...ux.intel.com,
linux-kernel@...r.kernel.org
Cc: dapeng1.mi@...ux.intel.com,
ak@...ux.intel.com,
zide.chen@...el.com,
mark.rutland@....com,
broonie@...nel.org,
ravi.bangoria@....com,
Kan Liang <kan.liang@...ux.intel.com>
Subject: [RFC PATCH V2 10/13] perf/x86: Add OPMASK into sample_simd_pred_reg
From: Kan Liang <kan.liang@...ux.intel.com>
The OPMASK is the SIMD's predicate registers. Add them into
sample_simd_pred_reg. The qwords of OPMASK is 1. There are 8 registers.
Signed-off-by: Kan Liang <kan.liang@...ux.intel.com>
---
arch/x86/events/core.c | 15 +++++++++++++++
arch/x86/events/perf_event.h | 1 +
arch/x86/include/asm/perf_event.h | 4 ++++
arch/x86/include/uapi/asm/perf_regs.h | 3 +++
arch/x86/kernel/perf_regs.c | 15 ++++++++++++---
5 files changed, 35 insertions(+), 3 deletions(-)
diff --git a/arch/x86/events/core.c b/arch/x86/events/core.c
index 3c05ca98ec3f..d4710edce2e9 100644
--- a/arch/x86/events/core.c
+++ b/arch/x86/events/core.c
@@ -427,6 +427,8 @@ static void x86_pmu_get_ext_regs(struct x86_perf_regs *perf_regs, u64 mask)
perf_regs->zmmh = get_xsave_addr(xsave, XFEATURE_ZMM_Hi256);
if (mask & XFEATURE_MASK_Hi16_ZMM)
perf_regs->h16zmm = get_xsave_addr(xsave, XFEATURE_Hi16_ZMM);
+ if (mask & XFEATURE_MASK_OPMASK)
+ perf_regs->opmask = get_xsave_addr(xsave, XFEATURE_OPMASK);
}
static void release_ext_regs_buffers(void)
@@ -459,6 +461,8 @@ static void reserve_ext_regs_buffers(void)
mask |= XFEATURE_MASK_ZMM_Hi256;
if (x86_pmu.ext_regs_mask & X86_EXT_REGS_H16ZMM)
mask |= XFEATURE_MASK_Hi16_ZMM;
+ if (x86_pmu.ext_regs_mask & X86_EXT_REGS_OPMASK)
+ mask |= XFEATURE_MASK_OPMASK;
size = xstate_calculate_size(mask, true);
@@ -1831,6 +1835,9 @@ void x86_pmu_setup_regs_data(struct perf_event *event,
data->dyn_size += hweight64(attr->sample_simd_vec_reg_user) *
sizeof(u64) *
attr->sample_simd_vec_reg_qwords;
+ data->dyn_size += hweight32(attr->sample_simd_pred_reg_user) *
+ sizeof(u64) *
+ attr->sample_simd_pred_reg_qwords;
data->regs_user.abi |= PERF_SAMPLE_REGS_ABI_SIMD;
}
perf_regs->abi = data->regs_user.abi;
@@ -1850,6 +1857,9 @@ void x86_pmu_setup_regs_data(struct perf_event *event,
data->dyn_size += hweight64(attr->sample_simd_vec_reg_intr) *
sizeof(u64) *
attr->sample_simd_vec_reg_qwords;
+ data->dyn_size += hweight32(attr->sample_simd_pred_reg_intr) *
+ sizeof(u64) *
+ attr->sample_simd_pred_reg_qwords;
data->regs_intr.abi |= PERF_SAMPLE_REGS_ABI_SIMD;
}
perf_regs->abi = data->regs_intr.abi;
@@ -1875,6 +1885,11 @@ void x86_pmu_setup_regs_data(struct perf_event *event,
perf_regs->h16zmm_regs = NULL;
mask |= XFEATURE_MASK_Hi16_ZMM;
}
+ if (attr->sample_simd_pred_reg_intr ||
+ attr->sample_simd_pred_reg_user) {
+ perf_regs->opmask_regs = NULL;
+ mask |= XFEATURE_MASK_OPMASK;
+ }
}
mask &= ~ignore_mask;
diff --git a/arch/x86/events/perf_event.h b/arch/x86/events/perf_event.h
index cc42e9d3e13d..cc0bd9479fa7 100644
--- a/arch/x86/events/perf_event.h
+++ b/arch/x86/events/perf_event.h
@@ -704,6 +704,7 @@ enum {
X86_EXT_REGS_YMM = BIT_ULL(1),
X86_EXT_REGS_ZMMH = BIT_ULL(2),
X86_EXT_REGS_H16ZMM = BIT_ULL(3),
+ X86_EXT_REGS_OPMASK = BIT_ULL(4),
};
#define PERF_PEBS_DATA_SOURCE_MAX 0x100
diff --git a/arch/x86/include/asm/perf_event.h b/arch/x86/include/asm/perf_event.h
index 2d78bd9649bd..dda677022882 100644
--- a/arch/x86/include/asm/perf_event.h
+++ b/arch/x86/include/asm/perf_event.h
@@ -609,6 +609,10 @@ struct x86_perf_regs {
u64 *h16zmm_regs;
struct avx_512_hi16_state *h16zmm;
};
+ union {
+ u64 *opmask_regs;
+ struct avx_512_opmask_state *opmask;
+ };
};
extern unsigned long perf_arch_instruction_pointer(struct pt_regs *regs);
diff --git a/arch/x86/include/uapi/asm/perf_regs.h b/arch/x86/include/uapi/asm/perf_regs.h
index f74e3ba65be2..dd7bd1dd8d39 100644
--- a/arch/x86/include/uapi/asm/perf_regs.h
+++ b/arch/x86/include/uapi/asm/perf_regs.h
@@ -55,11 +55,14 @@ enum perf_event_x86_regs {
#define PERF_REG_EXTENDED_MASK (~((1ULL << PERF_REG_X86_XMM0) - 1))
+#define PERF_X86_SIMD_PRED_REGS_MAX 8
+#define PERF_X86_SIMD_PRED_MASK GENMASK(PERF_X86_SIMD_PRED_REGS_MAX - 1, 0)
#define PERF_X86_SIMD_VEC_REGS_MAX 32
#define PERF_X86_SIMD_VEC_MASK GENMASK_ULL(PERF_X86_SIMD_VEC_REGS_MAX - 1, 0)
#define PERF_X86_H16ZMM_BASE 16
+#define PERF_X86_OPMASK_QWORDS 1
#define PERF_X86_XMM_QWORDS 2
#define PERF_X86_YMM_QWORDS 4
#define PERF_X86_YMMH_QWORDS (PERF_X86_YMM_QWORDS / 2)
diff --git a/arch/x86/kernel/perf_regs.c b/arch/x86/kernel/perf_regs.c
index 74e05e2e5c90..b569368743a4 100644
--- a/arch/x86/kernel/perf_regs.c
+++ b/arch/x86/kernel/perf_regs.c
@@ -82,8 +82,14 @@ u64 perf_simd_reg_value(struct pt_regs *regs, int idx,
{
struct x86_perf_regs *perf_regs = container_of(regs, struct x86_perf_regs, regs);
- if (pred)
- return 0;
+ if (pred) {
+ if (WARN_ON_ONCE(idx >= PERF_X86_SIMD_PRED_REGS_MAX ||
+ qwords_idx >= PERF_X86_OPMASK_QWORDS))
+ return 0;
+ if (!perf_regs->opmask_regs)
+ return 0;
+ return perf_regs->opmask_regs[idx];
+ }
if (WARN_ON_ONCE(idx >= PERF_X86_SIMD_VEC_REGS_MAX ||
qwords_idx >= PERF_X86_SIMD_QWORDS_MAX))
@@ -130,7 +136,10 @@ int perf_simd_reg_validate(u16 vec_qwords, u64 vec_mask,
if (vec_mask & ~PERF_X86_SIMD_VEC_MASK)
return -EINVAL;
}
- if (pred_mask)
+
+ if (pred_qwords != PERF_X86_OPMASK_QWORDS)
+ return -EINVAL;
+ if (pred_mask & ~PERF_X86_SIMD_PRED_MASK)
return -EINVAL;
return 0;
--
2.38.1
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