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Message-ID: <CAAQKjZOHUGg8WEZxfhVxrUPS3O68BQJ6=cDnUSk6BomYjuY62Q@mail.gmail.com>
Date: Fri, 27 Jun 2025 19:07:47 +0900
From: Inki Dae <daeinki@...il.com>
To: Kaustabh Chakraborty <kauschluss@...root.org>
Cc: Jagan Teki <jagan@...rulasolutions.com>, Marek Szyprowski <m.szyprowski@...sung.com>,
Andrzej Hajda <andrzej.hajda@...el.com>, Neil Armstrong <neil.armstrong@...aro.org>,
Robert Foss <rfoss@...nel.org>, Laurent Pinchart <Laurent.pinchart@...asonboard.com>,
Jonas Karlman <jonas@...boo.se>, Jernej Skrabec <jernej.skrabec@...il.com>,
Maarten Lankhorst <maarten.lankhorst@...ux.intel.com>, Maxime Ripard <mripard@...nel.org>,
Thomas Zimmermann <tzimmermann@...e.de>, David Airlie <airlied@...il.com>, Simona Vetter <simona@...ll.ch>,
Rob Herring <robh@...nel.org>, Krzysztof Kozlowski <krzk+dt@...nel.org>, Conor Dooley <conor+dt@...nel.org>,
Seung-Woo Kim <sw0312.kim@...sung.com>, Kyungmin Park <kyungmin.park@...sung.com>,
Krzysztof Kozlowski <krzk@...nel.org>, Alim Akhtar <alim.akhtar@...sung.com>,
dri-devel@...ts.freedesktop.org, linux-kernel@...r.kernel.org,
devicetree@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
linux-samsung-soc@...r.kernel.org
Subject: Re: [PATCH v2 01/13] drm/bridge: samsung-dsim: separate LINK and DPHY
status registers
2025년 6월 27일 (금) 오전 4:42, Kaustabh Chakraborty <kauschluss@...root.org>님이 작성:
>
> Exynos7870's DSIM has separate registers for LINK and DPHY status. This
> is in contrast to other devices in the driver which use a single
> register for both.
>
> Add their respective entries in the register list. Devices having a
> single status register have been assigned the same offset for both
> entries.
>
> Signed-off-by: Kaustabh Chakraborty <kauschluss@...root.org>
> ---
> drivers/gpu/drm/bridge/samsung-dsim.c | 15 +++++++++------
> 1 file changed, 9 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/bridge/samsung-dsim.c b/drivers/gpu/drm/bridge/samsung-dsim.c
> index f2f666b27d2d5ec016d7a7f47c87fcdf1377d41a..7fd4c34cdc3170d363942f98feec048097da3c06 100644
> --- a/drivers/gpu/drm/bridge/samsung-dsim.c
> +++ b/drivers/gpu/drm/bridge/samsung-dsim.c
> @@ -30,7 +30,7 @@
> /* returns true iff both arguments logically differs */
> #define NEQV(a, b) (!(a) ^ !(b))
>
> -/* DSIM_STATUS */
> +/* DSIM_DPHY_STATUS */
> #define DSIM_STOP_STATE_DAT(x) (((x) & 0xf) << 0)
> #define DSIM_STOP_STATE_CLK BIT(8)
> #define DSIM_TX_READY_HS_CLK BIT(10)
> @@ -239,7 +239,8 @@ enum samsung_dsim_transfer_type {
> };
>
> enum reg_idx {
> - DSIM_STATUS_REG, /* Status register */
According to the datasheets I have, both Exynos5422 and Exynos7420 use
DSIM_STATUS, while Exynos8890 splits this into DSIM_LINK_STATUS and
DSIM_PHY_STATUS. It appears that Exynos7870 follows the same approach
as Exynos8890.
The current modification removes the legacy DSIM_STATUS_REG and adds
new DSIM_LINK_STATUS_REG and DSIM_DPHY_STATUS_REG. However, this
change causes the register names used for older SoC versions to differ
from those in the datasheets, so I think it is better to keep the
legacy name for backward compatibility.
How about modifying it as follows?
enum reg_idx {
DSIM_STATUS_REG, /* Status register (legacy) */
DSIM_LINK_STATUS_REG, /* Link status register (Exynos7870, ...) */
DSIM_PHY_STATUS_REG, /* PHY status register (Exynos7870, ...) */
...
};
static const unsigned int exynos7870_reg_ofs[] = {
[DSIM_STATUS_REG] = 0x00, /* Legacy compatibility - use
LINK_STATUS */
[DSIM_LINK_STATUS_REG] = 0x04, /* Link status register */
[DSIM_PHY_STATUS_REG] = 0x08, /* PHY status register */
...
};
Additionally, by configuring the hw_type field in the
samsung_dsim_plat_data structure like you did with the patch[1], you
can use the appropriate register name for each SoC as shown below:
if (dsi->plat_data->hw_type == DSIM_TYPE_EXYNOS7870)
reg = samsung_dsim_read(dsi, DSIM_LINK_STATUS_REG);
else
reg = samsung_dsim_read(dsi, DSIM_STATUS_REG);
[1] [PATCH v2 12/13] drm/bridge: samsung-dsim: add driver support for
exynos7870 DSIM bridge
Thanks,
Inki Dae
> + DSIM_LINK_STATUS_REG, /* Link status register */
> + DSIM_DPHY_STATUS_REG, /* D-PHY status register */
> DSIM_SWRST_REG, /* Software reset register */
> DSIM_CLKCTRL_REG, /* Clock control register */
> DSIM_TIMEOUT_REG, /* Time out register */
> @@ -264,7 +265,8 @@ enum reg_idx {
> };
>
> static const unsigned int exynos_reg_ofs[] = {
> - [DSIM_STATUS_REG] = 0x00,
> + [DSIM_LINK_STATUS_REG] = 0x00,
> + [DSIM_DPHY_STATUS_REG] = 0x00,
> [DSIM_SWRST_REG] = 0x04,
> [DSIM_CLKCTRL_REG] = 0x08,
> [DSIM_TIMEOUT_REG] = 0x0c,
> @@ -288,7 +290,8 @@ static const unsigned int exynos_reg_ofs[] = {
> };
>
> static const unsigned int exynos5433_reg_ofs[] = {
> - [DSIM_STATUS_REG] = 0x04,
> + [DSIM_LINK_STATUS_REG] = 0x04,
> + [DSIM_DPHY_STATUS_REG] = 0x04,
> [DSIM_SWRST_REG] = 0x0C,
> [DSIM_CLKCTRL_REG] = 0x10,
> [DSIM_TIMEOUT_REG] = 0x14,
> @@ -690,7 +693,7 @@ static unsigned long samsung_dsim_set_pll(struct samsung_dsim *dsi,
> dev_err(dsi->dev, "PLL failed to stabilize\n");
> return 0;
> }
> - reg = samsung_dsim_read(dsi, DSIM_STATUS_REG);
> + reg = samsung_dsim_read(dsi, DSIM_LINK_STATUS_REG);
> } while ((reg & DSIM_PLL_STABLE) == 0);
>
> dsi->hs_clock = fout;
> @@ -966,7 +969,7 @@ static int samsung_dsim_init_link(struct samsung_dsim *dsi)
> return -EFAULT;
> }
>
> - reg = samsung_dsim_read(dsi, DSIM_STATUS_REG);
> + reg = samsung_dsim_read(dsi, DSIM_DPHY_STATUS_REG);
> if ((reg & DSIM_STOP_STATE_DAT(lanes_mask))
> != DSIM_STOP_STATE_DAT(lanes_mask))
> continue;
>
> --
> 2.49.0
>
>
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