linux-kernel - Re: [PATCH v8 3/4] phy: rockchip-pcie: Enable all four lanes if required

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Message-ID: <4006908.X513TT2pbd@diego>
Date: Mon, 30 Jun 2025 23:33:19 +0200
From: Heiko Stübner <heiko@...ech.de>
To: linux-rockchip@...ts.infradead.org,
 Geraldo Nascimento <geraldogabriel@...il.com>
Cc: Shawn Lin <shawn.lin@...k-chips.com>,
 Lorenzo Pieralisi <lpieralisi@...nel.org>,
 Krzysztof Wilczyński <kw@...ux.com>,
 Manivannan Sadhasivam <mani@...nel.org>, Rob Herring <robh@...nel.org>,
 Bjorn Helgaas <bhelgaas@...gle.com>, Vinod Koul <vkoul@...nel.org>,
 Kishon Vijay Abraham I <kishon@...nel.org>,
 Rick wertenbroek <rick.wertenbroek@...il.com>,
 Neil Armstrong <neil.armstrong@...aro.org>,
 Valmantas Paliksa <walmis@...il.com>, linux-phy@...ts.infradead.org,
 linux-pci@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
 linux-kernel@...r.kernel.org
Subject:
 Re: [PATCH v8 3/4] phy: rockchip-pcie: Enable all four lanes if required

Am Montag, 30. Juni 2025, 20:22:01 Mitteleuropäische Sommerzeit schrieb Geraldo Nascimento:
> Current code enables only Lane 0 because pwr_cnt will be incremented on
> first call to the function. Let's reorder the enablement code to enable
> all 4 lanes through GRF.
> 
> Reviewed-by: Neil Armstrong <neil.armstrong@...aro.org>
> Reviewed-by: Robin Murphy <robin.murphy@....com>
> 
> Signed-off-by: Valmantas Paliksa <walmis@...il.com>
> Signed-off-by: Geraldo Nascimento <geraldogabriel@...il.com>

hmm, if Valmantas is the original author you should probably keep that authorship
  git commit --amend --author="Valmantas Paliksa <walmis@...il.com>"
should do the trick.

The first signed-off should be from the patch author, then your signed-off
indicates you handling the patch later as part of this series.

[or, if you modified the code of the patch heavily, Co-developed-by could
 also be appropriate]

Heiko

> ---
>  drivers/phy/rockchip/phy-rockchip-pcie.c | 12 ++++++------
>  1 file changed, 6 insertions(+), 6 deletions(-)
> 
> diff --git a/drivers/phy/rockchip/phy-rockchip-pcie.c b/drivers/phy/rockchip/phy-rockchip-pcie.c
> index bd44af36c67a..f22ffb41cdc2 100644
> --- a/drivers/phy/rockchip/phy-rockchip-pcie.c
> +++ b/drivers/phy/rockchip/phy-rockchip-pcie.c
> @@ -160,6 +160,12 @@ static int rockchip_pcie_phy_power_on(struct phy *phy)
>  
>  	guard(mutex)(&rk_phy->pcie_mutex);
>  
> +	regmap_write(rk_phy->reg_base,
> +		     rk_phy->phy_data->pcie_laneoff,
> +		     HIWORD_UPDATE(!PHY_LANE_IDLE_OFF,
> +				   PHY_LANE_IDLE_MASK,
> +				   PHY_LANE_IDLE_A_SHIFT + inst->index));
> +
>  	if (rk_phy->pwr_cnt++) {
>  		return 0;
>  	}
> @@ -176,12 +182,6 @@ static int rockchip_pcie_phy_power_on(struct phy *phy)
>  				   PHY_CFG_ADDR_MASK,
>  				   PHY_CFG_ADDR_SHIFT));
>  
> -	regmap_write(rk_phy->reg_base,
> -		     rk_phy->phy_data->pcie_laneoff,
> -		     HIWORD_UPDATE(!PHY_LANE_IDLE_OFF,
> -				   PHY_LANE_IDLE_MASK,
> -				   PHY_LANE_IDLE_A_SHIFT + inst->index));
> -
>  	/*
>  	 * No documented timeout value for phy operation below,
>  	 * so we make it large enough here. And we use loop-break
>