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Message-ID: <CAMuHMdUrkcxr+_jcr-F76cOg+rie3c2FcrEpfrH36kKJFhF9vw@mail.gmail.com>
Date: Mon, 30 Jun 2025 10:10:09 +0200
From: Geert Uytterhoeven <geert@...ux-m68k.org>
To: Prabhakar <prabhakar.csengg@...il.com>
Cc: Greg Kroah-Hartman <gregkh@...uxfoundation.org>, Jiri Slaby <jirislaby@...nel.org>, 
	Rob Herring <robh@...nel.org>, Krzysztof Kozlowski <krzk+dt@...nel.org>, Conor Dooley <conor+dt@...nel.org>, 
	Magnus Damm <magnus.damm@...il.com>, Wolfram Sang <wsa+renesas@...g-engineering.com>, 
	linux-serial@...r.kernel.org, devicetree@...r.kernel.org, 
	linux-kernel@...r.kernel.org, linux-renesas-soc@...r.kernel.org, 
	Biju Das <biju.das.jz@...renesas.com>, 
	Fabrizio Castro <fabrizio.castro.jz@...esas.com>, 
	Lad Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com>
Subject: Re: [PATCH v13 1/5] dt-bindings: serial: renesas,rsci: Add optional
 secondary clock input

Hi Prabhakar,

On Sat, 28 Jun 2025 at 13:57, Prabhakar <prabhakar.csengg@...il.com> wrote:
> From: Thierry Bultel <thierry.bultel.yh@...renesas.com>
>
> Update the RSCI binding to support an optional secondary clock input on
> the RZ/T2H SoC. At boot, the RSCI operates using the default synchronous
> clock (PCLKM core clock), which is enabled by the bootloader. However, to
> support a wider range of baud rates, the hardware also requires an
> asynchronous external clock input. Clock selection is controlled
> internally by the CCR3 register in the RSCI block.
>
> Due to an incomplete understanding of the hardware, the original binding
> defined only a single clock ("fck"), which is insufficient to describe the
> full capabilities of the RSCI on RZ/T2H. This update corrects the binding
> by allowing up to three clocks and defining the `clock-names` as
> "operation", "bus", and optionally "sck" for the asynchronous clock input.
>
> This is an ABI change, as it modifies the expected number and names of
> clocks. However, since there are no in-kernel consumers of this binding
> yet, the change is considered safe and non-disruptive.
>
> Also remove the unneeded `serial0` alias from the DTS example and use
> the R9A09G077_CLK_PCLKM macro for core clock.
>
> Signed-off-by: Thierry Bultel <thierry.bultel.yh@...renesas.com>
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com>
> Reviewed-by: Geert Uytterhoeven <geert+renesas@...der.be>
> ---
> v12->v13:
> - Rebased on latest linux-next.
> - Updated commit message to clarify the ABI change.

Thanks for the update!

> - Used `R9A09G077_CLK_PCLKM` macro for core clock

Unfortunately include/dt-bindings/clock/renesas,r9a09g077-cpg-mssr.h
is not yet upstream, so you cannot use its definitions yet outside
renesas-clk.

> --- a/Documentation/devicetree/bindings/serial/renesas,rsci.yaml
> +++ b/Documentation/devicetree/bindings/serial/renesas,rsci.yaml

> @@ -63,12 +68,8 @@ unevaluatedProperties: false
>
>  examples:
>    - |
> +    #include <dt-bindings/clock/renesas,r9a09g077-cpg-mssr.h>
>      #include <dt-bindings/interrupt-controller/arm-gic.h>
> -    #include <dt-bindings/clock/renesas-cpg-mssr.h>
> -
> -    aliases {
> -        serial0 = &sci0;
> -    };
>
>      sci0: serial@...05000 {
>          compatible = "renesas,r9a09g077-rsci";
> @@ -78,7 +79,7 @@ examples:
>                       <GIC_SPI 592 IRQ_TYPE_EDGE_RISING>,
>                       <GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>;
>          interrupt-names = "eri", "rxi", "txi", "tei";
> -        clocks = <&cpg CPG_MOD 108>;
> -        clock-names = "fck";
> +        clocks = <&cpg CPG_MOD 8>, <&cpg CPG_CORE R9A09G077_CLK_PCLKM>;
> +        clock-names = "operation", "bus";
>          power-domains = <&cpg>;
>      };

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@...ux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

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