lists.openwall.net   lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  linux-cve-announce  PHC 
Open Source and information security mailing list archives
 
Hash Suite: Windows password security audit tool. GUI, reports in PDF.
[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-ID: <36b3528e-9110-f027-4dff-4a3dfc38364e@linux.intel.com>
Date: Mon, 30 Jun 2025 14:25:41 +0300 (EEST)
From: Ilpo Järvinen <ilpo.jarvinen@...ux.intel.com>
To: Xi Pardee <xi.pardee@...ux.intel.com>
cc: irenic.rajneesh@...il.com, david.e.box@...ux.intel.com, 
    hdegoede@...hat.com, ilpo.jarvinen@...ux.intel.com, 
    platform-driver-x86@...r.kernel.org, linux-kernel@...r.kernel.org, 
    linux-pm@...r.kernel.org
Subject: Re: [PATCH v2 1/5] platform/x86:intel/pmc: Enable SSRAM support for
 Lunar Lake

On Tue, 24 Jun 2025, Xi Pardee wrote:

> Enable Lunar Lake platforms to achieve PMC information from
> Intel PMC SSRAM Telemetry driver and substate requirements data
> from telemetry region.
> 
> Signed-off-by: Xi Pardee <xi.pardee@...ux.intel.com>
> ---
>  drivers/platform/x86/intel/pmc/lnl.c | 16 ++++++++++++++++
>  1 file changed, 16 insertions(+)
> 
> diff --git a/drivers/platform/x86/intel/pmc/lnl.c b/drivers/platform/x86/intel/pmc/lnl.c
> index da513c234714b..e08a77c778c2c 100644
> --- a/drivers/platform/x86/intel/pmc/lnl.c
> +++ b/drivers/platform/x86/intel/pmc/lnl.c
> @@ -13,6 +13,10 @@
>  
>  #include "core.h"
>  
> +#define SOCM_LPM_REQ_GUID	0x15099748
> +
> +static const u8 LNL_LPM_REG_INDEX[] = {0, 4, 5, 6, 8, 9, 10, 11, 12, 13, 14, 15, 16, 20};
> +
>  static const struct pmc_bit_map lnl_ltr_show_map[] = {
>  	{"SOUTHPORT_A",		CNP_PMC_LTR_SPA},
>  	{"SOUTHPORT_B",		CNP_PMC_LTR_SPB},
> @@ -528,6 +532,16 @@ static const struct pmc_reg_map lnl_socm_reg_map = {
>  	.lpm_live_status_offset = MTL_LPM_LIVE_STATUS_OFFSET,
>  	.s0ix_blocker_maps = lnl_blk_maps,
>  	.s0ix_blocker_offset = LNL_S0IX_BLOCKER_OFFSET,
> +	.lpm_reg_index = LNL_LPM_REG_INDEX,
> +};
> +
> +static struct pmc_info lnl_pmc_info_list[] = {
> +	{
> +		.guid	= SOCM_LPM_REQ_GUID,
> +		.devid	= PMC_DEVID_LNL_SOCM,
> +		.map	= &lnl_socm_reg_map,
> +	},
> +	{}
>  };
>  
>  #define LNL_NPU_PCI_DEV		0x643e
> @@ -557,6 +571,8 @@ static int lnl_core_init(struct pmc_dev *pmcdev, struct pmc_dev_info *pmc_dev_in
>  }
>  
>  struct pmc_dev_info lnl_pmc_dev = {
> +	.pci_func = 2,
> +	.regmap_list = lnl_pmc_info_list,
>  	.map = &lnl_socm_reg_map,
>  	.suspend = cnl_suspend,
>  	.resume = lnl_resume,
> 

Reviewed-by: Ilpo Järvinen <ilpo.jarvinen@...ux.intel.com>

-- 
 i.

Powered by blists - more mailing lists

Powered by Openwall GNU/*/Linux Powered by OpenVZ