linux-kernel - Re: [PATCH 5/5] drm/sun4i: Run the mixer clock at 297 MHz on V3s

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Message-ID: <4bc1c1fd9aa1e97a04d964fc5601155ade52cd2d.camel@icenowy.me>
Date: Wed, 02 Jul 2025 10:52:10 +0800
From: Icenowy Zheng <uwu@...nowy.me>
To: Paul Kocialkowski <paulk@...-base.io>, linux-media@...r.kernel.org, 
	devicetree@...r.kernel.org, linux-arm-kernel@...ts.infradead.org, 
	linux-sunxi@...ts.linux.dev, linux-kernel@...r.kernel.org, 
	linux-clk@...r.kernel.org, dri-devel@...ts.freedesktop.org, 
	linux-gpio@...r.kernel.org
Cc: Yong Deng <yong.deng@...ewell.com>, Rob Herring <robh@...nel.org>, 
 Krzysztof Kozlowski <krzk+dt@...nel.org>, Conor Dooley
 <conor+dt@...nel.org>, Chen-Yu Tsai <wens@...e.org>, Jernej Skrabec
 <jernej.skrabec@...il.com>, Samuel Holland <samuel@...lland.org>, Michael
 Turquette <mturquette@...libre.com>, Stephen Boyd <sboyd@...nel.org>,
 Maxime Ripard <mripard@...nel.org>, Maarten Lankhorst
 <maarten.lankhorst@...ux.intel.com>, Thomas Zimmermann
 <tzimmermann@...e.de>,  David Airlie <airlied@...il.com>, Simona Vetter
 <simona@...ll.ch>, Linus Walleij <linus.walleij@...aro.org>,  Icenowy Zheng
 <icenowy@...c.xyz>, Andre Przywara <andre.przywara@....com>
Subject: Re: [PATCH 5/5] drm/sun4i: Run the mixer clock at 297 MHz on V3s

在 2025-07-01星期二的 22:11 +0200，Paul Kocialkowski写道：
> The DE mixer clock is currently set to run at 150 MHz, while the
> Allwinner BSP configures it at 300 MHz and other platforms typically
> run at 297 MHz.
> 
> 150 MHz appears to be enough given the restricted graphics
> capabilities
> of the SoC (with a work area of only 1024x1024). However it typically
> causes the DE clock to be parented to the periph0 pll instead of the
> video PLL.
> 
> While this should generally not be a concern, it appears (based on
> experimentation) that both the DE and TCON clocks need to be parented
> to the same PLL for these units to work. While we cannot represent
> this
> constraint in the clock driver, it appears that the TCON clock will
> often get parented to the video pll (typically running at 297 MHz for

Ah I think pixel clocks are arbitary and nothing could be predicted
about it...

> the CSI units needs), for instance when driving displays with a 33
> MHz
> pixel clock (33 being a natural divider of 297).
> 
> Running the DE clock at 297 MHz will typically result in parenting to
> the video pll instead of the periph0 pll, thus making the display
> output functional.
> 
> This is all a bit fragile but it solves the issue with displays
> running
> at 33 Mhz and brings V3s to use the same frequency as other
> platforms,
> making support more unified.
> 
> Also align and sort the fields of the v3s mixer config while at it.
> 
> Signed-off-by: Paul Kocialkowski <paulk@...-base.io>
> ---
>  drivers/gpu/drm/sun4i/sun8i_mixer.c | 12 ++++++------
>  1 file changed, 6 insertions(+), 6 deletions(-)
> 
> diff --git a/drivers/gpu/drm/sun4i/sun8i_mixer.c
> b/drivers/gpu/drm/sun4i/sun8i_mixer.c
> index 8b41d33baa30..35fdc2451060 100644
> --- a/drivers/gpu/drm/sun4i/sun8i_mixer.c
> +++ b/drivers/gpu/drm/sun4i/sun8i_mixer.c
> @@ -670,12 +670,12 @@ static const struct sun8i_mixer_cfg
> sun8i_r40_mixer1_cfg = {
>  };
>  
>  static const struct sun8i_mixer_cfg sun8i_v3s_mixer_cfg = {
> -       .vi_num = 2,
> -       .ui_num = 1,
> -       .scaler_mask = 0x3,
> -       .scanline_yuv = 2048,
> -       .ccsc = CCSC_MIXER0_LAYOUT,
> -       .mod_rate = 150000000,
> +       .ccsc           = CCSC_MIXER0_LAYOUT,
> +       .mod_rate       = 297000000,
> +       .scaler_mask    = 0x3,
> +       .scanline_yuv   = 2048,
> +       .ui_num         = 1,
> +       .vi_num         = 2,
>  };
>  
>  static const struct sun8i_mixer_cfg sun20i_d1_mixer0_cfg = {