linux-kernel - Re: [PATCH net-next v12 09/14] dpll: zl3073x: Register DPLL devices and pins

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Message-ID: <1848e2f6-a0bb-48e6-9bfc-5ea6cbea2e5c@redhat.com>
Date: Wed, 2 Jul 2025 13:49:22 +0200
From: Ivan Vecera <ivecera@...hat.com>
To: Jiri Pirko <jiri@...nulli.us>
Cc: netdev@...r.kernel.org, Prathosh Satish <Prathosh.Satish@...rochip.com>,
 Vadim Fedorenko <vadim.fedorenko@...ux.dev>,
 Arkadiusz Kubalewski <arkadiusz.kubalewski@...el.com>,
 Rob Herring <robh@...nel.org>, Krzysztof Kozlowski <krzk+dt@...nel.org>,
 Conor Dooley <conor+dt@...nel.org>, "David S. Miller" <davem@...emloft.net>,
 Eric Dumazet <edumazet@...gle.com>, Jakub Kicinski <kuba@...nel.org>,
 Paolo Abeni <pabeni@...hat.com>, Simon Horman <horms@...nel.org>,
 Jonathan Corbet <corbet@....net>, Jason Gunthorpe <jgg@...pe.ca>,
 Shannon Nelson <shannon.nelson@....com>, Dave Jiang <dave.jiang@...el.com>,
 Jonathan Cameron <Jonathan.Cameron@...wei.com>, devicetree@...r.kernel.org,
 linux-kernel@...r.kernel.org, linux-doc@...r.kernel.org,
 Michal Schmidt <mschmidt@...hat.com>, Petr Oros <poros@...hat.com>
Subject: Re: [PATCH net-next v12 09/14] dpll: zl3073x: Register DPLL devices
 and pins

On 02. 07. 25 12:57 odp., Jiri Pirko wrote:
> Sun, Jun 29, 2025 at 09:10:44PM +0200, ivecera@...hat.com wrote:
> 
> [...]
> 
>> +/**
>> + * zl3073x_dpll_device_register - register DPLL device
>> + * @zldpll: pointer to zl3073x_dpll structure
>> + *
>> + * Registers given DPLL device into DPLL sub-system.
>> + *
>> + * Return: 0 on success, <0 on error
>> + */
>> +static int
>> +zl3073x_dpll_device_register(struct zl3073x_dpll *zldpll)
>> +{
>> +	struct zl3073x_dev *zldev = zldpll->dev;
>> +	u8 dpll_mode_refsel;
>> +	int rc;
>> +
>> +	/* Read DPLL mode and forcibly selected reference */
>> +	rc = zl3073x_read_u8(zldev, ZL_REG_DPLL_MODE_REFSEL(zldpll->id),
>> +			     &dpll_mode_refsel);
>> +	if (rc)
>> +		return rc;
>> +
>> +	/* Extract mode and selected input reference */
>> +	zldpll->refsel_mode = FIELD_GET(ZL_DPLL_MODE_REFSEL_MODE,
>> +					dpll_mode_refsel);
> 
> Who sets this?

WDYM? refsel_mode register? If so this register is populated from
configuration stored in flash inside the chip. And the configuration
is prepared by vendor/OEM.

>> +	zldpll->forced_ref = FIELD_GET(ZL_DPLL_MODE_REFSEL_REF,
>> +				       dpll_mode_refsel);
>> +
>> +	zldpll->dpll_dev = dpll_device_get(zldev->clock_id, zldpll->id,
>> +					   THIS_MODULE);
>> +	if (IS_ERR(zldpll->dpll_dev)) {
>> +		rc = PTR_ERR(zldpll->dpll_dev);
>> +		zldpll->dpll_dev = NULL;
>> +
>> +		return rc;
>> +	}
>> +
>> +	rc = dpll_device_register(zldpll->dpll_dev,
>> +				  zl3073x_prop_dpll_type_get(zldev, zldpll->id),
>> +				  &zl3073x_dpll_device_ops, zldpll);
>> +	if (rc) {
>> +		dpll_device_put(zldpll->dpll_dev);
>> +		zldpll->dpll_dev = NULL;
>> +	}
>> +
>> +	return rc;
>> +}
> 
> [...]
>