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Message-ID: <klhvgzizub33f46buqsog54wqksqp24a5tijwyv355l2ao2imo@wdkojfebc6s2>
Date: Fri, 4 Jul 2025 00:23:27 +0300
From: Dmitry Baryshkov <dmitry.baryshkov@....qualcomm.com>
To: Bryan O'Donoghue <bryan.odonoghue@...aro.org>
Cc: Konrad Dybcio <konrad.dybcio@....qualcomm.com>,
Krzysztof Kozlowski <krzk@...nel.org>,
Vikash Garodia <quic_vgarodia@...cinc.com>,
Dikshita Agarwal <quic_dikshita@...cinc.com>,
Abhinav Kumar <abhinav.kumar@...ux.dev>,
Mauro Carvalho Chehab <mchehab@...nel.org>,
Rob Herring <robh@...nel.org>,
Krzysztof Kozlowski <krzk+dt@...nel.org>,
Conor Dooley <conor+dt@...nel.org>, linux-media@...r.kernel.org,
linux-arm-msm@...r.kernel.org, devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org
Subject: Re: [PATCH v3 0/5] Introduce "non-pixel" sub node within iris video
node
On Thu, Jul 03, 2025 at 09:28:12PM +0100, Bryan O'Donoghue wrote:
> On 03/07/2025 16:28, Konrad Dybcio wrote:
> > Back to the point, I actually think what this patchset does is
> > resonable, especially given the address range and SMMU SID requirements
> > that the OS*must* be aware of (or the device will crash after a
> > translation fault / security violation).
>
> I still give my RB for the series.
>
> To me the only question is should it be applied to sm8550 or to new SoCs
> from now on, sa8775p, x1e and derivatives.
I think we need to apply it to _all_ SoCs, maybe starting from MSM8x26
and MSM8x16. Likewise, we need to think bout secure buffers usecase. And
once we do that, we will realize that it also changes the ABI for all
SoCs that support either Venus or Iris.
> I take the point on ABI breakage on 8550, so to me it seems fully consistent
> with Krzysztof's statements on ABI maintenance and indeed the need to expand
> the features of this driver to do so from the next submission onwards.
>
> That can be as simple as
>
> schema.yaml
>
> if compatible newsoc
> minItems:1
> maxItems:2
>
> 8550's ABI is stable and new SoC submissions will support the
> secure/non-pixel method.
--
With best wishes
Dmitry
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