linux-kernel - [PATCH v2 0/1] irqchip/gic-v3: Add Altera Agilex5 address bus

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Message-ID: <cover.1751618484.git.adrianhoyin.ng@altera.com>
Date: Fri,  4 Jul 2025 16:49:49 +0800
From: adrianhoyin.ng@...era.com
To: maz@...nel.org,
	tglx@...utronix.de,
	catalin.marinas@....com,
	will@...nel.org,
	linux-arm-kernel@...ts.infradead.org,
	linux-kernel@...r.kernel.org
Cc: adrianhoyin.ng@...era.com
Subject: [PATCH v2 0/1] irqchip/gic-v3: Add Altera Agilex5 address bus

From: Adrian Ng Ho Yin <adrianhoyin.ng@...era.com>

Agilex5 address bus width for the ACE-lite interface is only 32 bits.
Hence the GIC600 SoC integration for Agilex5 can only access the first
32bit of the physical address space.

Add quirk to configure the gfp flag to allocate memory within 32bit
addressable range. As the 0x0201743b GIC600 ID is not specific to
Altera, of_machine_is_compatible() is added.

Add config in arm64 Kconfig to enable quirk.

change log:
v2: - Reworked implementation to reuse existing infrastructure as
      requested by Marc Zyngier.

    - Add new config in arm64 Kconfig to enable quirk.

    - Dropped dt and binding changes.
---
v1: - https://lore.kernel.org/all/cover.1747368554.git.adrianhoyin.ng@altera.com/

Adrian Ng Ho Yin (1):
  irqchip/gic-v3: Add Altera Agilex5 address bus width limitation
    workaround

 arch/arm64/Kconfig               | 10 ++++++++++
 drivers/irqchip/irq-gic-v3-its.c | 18 ++++++++++++++++++
 2 files changed, 28 insertions(+)

-- 
2.49.GIT