linux-kernel - [PATCH v2 1/1] irqchip/gic-v3: Add Altera Agilex5 address bus width limitation workaround

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-ID: <6a44509ca0edaabc17e59d2e27fef1c782183456.1751618484.git.adrianhoyin.ng@altera.com>
Date: Fri,  4 Jul 2025 16:49:50 +0800
From: adrianhoyin.ng@...era.com
To: maz@...nel.org,
	tglx@...utronix.de,
	catalin.marinas@....com,
	will@...nel.org,
	linux-arm-kernel@...ts.infradead.org,
	linux-kernel@...r.kernel.org
Cc: adrianhoyin.ng@...era.com
Subject: [PATCH v2 1/1] irqchip/gic-v3: Add Altera Agilex5 address bus width limitation workaround

From: Adrian Ng Ho Yin <adrianhoyin.ng@...era.com>

Agilex5 address bus width for the ACE-lite interface is only 32 bits.
Hence the GIC600 SoC integration for Agilex5 can only access the first
32bit of the physical address space.

Add quirk to configure the gfp flag to allocate memory within 32bit
addressable range. As the 0x0201743b GIC600 ID is not specific to
Altera, of_machine_is_compatible() is added.

Signed-off-by: Adrian Ng Ho Yin <adrianhoyin.ng@...era.com>
---
 arch/arm64/Kconfig               | 10 ++++++++++
 drivers/irqchip/irq-gic-v3-its.c | 18 ++++++++++++++++++
 2 files changed, 28 insertions(+)

diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig
index 55fc331af337..2286b4d378e2 100644
--- a/arch/arm64/Kconfig
+++ b/arch/arm64/Kconfig
@@ -1348,6 +1348,16 @@ config SOCIONEXT_SYNQUACER_PREITS
 
 	  If unsure, say Y.
 
+config ALTERA_AGILEX5_ADDR_BUS_WIDTH_LIMITATION
+	bool "Altera Agilex: GIC600 can not access physical addresses higher than 4GB"
+	default y
+	help
+	  Agilex5 address bus width for the ACE-lite interface is only 32 bits. Hence
+	  the GIC600 SoC integration for Agilex5 can only access the first 32bit of the
+	  physical address space.
+
+	  If unsure, say Y.
+
 endmenu # "ARM errata workarounds via the alternatives framework"
 
 choice
diff --git a/drivers/irqchip/irq-gic-v3-its.c b/drivers/irqchip/irq-gic-v3-its.c
index d54fa0638dc4..a2cf401568e7 100644
--- a/drivers/irqchip/irq-gic-v3-its.c
+++ b/drivers/irqchip/irq-gic-v3-its.c
@@ -4901,6 +4901,16 @@ static bool __maybe_unused its_enable_rk3568002(void *data)
 	return true;
 }
 
+static bool __maybe_unused its_enable_agilex5(void *data)
+{
+	if (!of_machine_is_compatible("intel,socfpga-agilex5"))
+		return false;
+
+	gfp_flags_quirk |= GFP_DMA32;
+
+	return true;
+}
+
 static const struct gic_quirk its_quirks[] = {
 #ifdef CONFIG_CAVIUM_ERRATUM_22375
 	{
@@ -4975,6 +4985,14 @@ static const struct gic_quirk its_quirks[] = {
 		.mask   = 0xffffffff,
 		.init   = its_enable_rk3568002,
 	},
+#endif
+#ifdef ALTERA_AGILEX5_ADDR_BUS_WIDTH_LIMITATION
+	{
+		.desc   = "ITS: Altera Agilex5 address bus width limitation",
+		.iidr   = 0x0201743b,
+		.mask   = 0xffffffff,
+		.init   = its_enable_agilex5,
+	},
 #endif
 	{
 	}
-- 
2.49.GIT