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Message-ID: <031be49c-b079-40c3-af92-7ab3abeec6b3@linux.dev>
Date: Sat, 5 Jul 2025 00:43:36 -0700
From: Atish Patra <atish.patra@...ux.dev>
To: Anup Patel <apatel@...tanamicro.com>
Cc: Palmer Dabbelt <palmer@...belt.com>,
 Paul Walmsley <paul.walmsley@...ive.com>, Alexandre Ghiti <alex@...ti.fr>,
 Andrew Jones <ajones@...tanamicro.com>, Anup Patel <anup@...infault.org>,
 kvm@...r.kernel.org, kvm-riscv@...ts.infradead.org,
 linux-riscv@...ts.infradead.org, linux-kernel@...r.kernel.org
Subject: Re: [PATCH 0/2] Few timer and AIA fixes for KVM RISC-V


On 7/4/25 8:38 AM, Anup Patel wrote:
> The RISC-V Privileged specificaiton says the following: "WFI is also
> required to resume execution for locally enabled interrupts pending
> at any privilege level, regardless of the global interrupt enable at
> each privilege level."
>
> Based on the above, if there is pending VS-timer interrupt when the
> host (aka HS-mode) executes WFI then such a WFI will simply become NOP
> and not do anything. This result in QEMU RISC-V consuming a lot of CPU
> time on the x86 machine where it is running. The PATCH1 solves this
> issue by adding appropriate cleanup in KVM RISC-V timer virtualization.
>
> As a result PATCH1, race conditions in updating HGEI[E|P] CSRs when a
> VCPU is moved from one host CPU to another are being observed on QEMU
> so the PATCH2 tries to minimize the chances of these race conditions.
>
> Anup Patel (2):
>    RISC-V: KVM: Disable vstimecmp before exiting to user-space
>    RISC-V: KVM: Move HGEI[E|P] CSR access to IMSIC virtualization
>
>   arch/riscv/include/asm/kvm_aia.h |  4 ++-
>   arch/riscv/kvm/aia.c             | 51 +++++---------------------------
>   arch/riscv/kvm/aia_imsic.c       | 45 ++++++++++++++++++++++++++++
>   arch/riscv/kvm/vcpu.c            |  2 --
>   arch/riscv/kvm/vcpu_timer.c      | 16 ++++++++++
>   5 files changed, 71 insertions(+), 47 deletions(-)
>
For the entire series :

Tested-by: Atish Patra <atishp@...osinc.com>

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