linux-kernel - Re: [PATCH v2 07/10] dt-bindings: phy: Add PHY bindings support for FSD SoC

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Message-ID: <a2fec2cf-46e2-4436-adc2-8f555a558929@kernel.org>
Date: Sat, 5 Jul 2025 09:47:56 +0200
From: Krzysztof Kozlowski <krzk@...nel.org>
To: Pankaj Dubey <pankaj.dubey@...sung.com>,
 'Shradha Todi' <shradha.t@...sung.com>, 'Rob Herring' <robh@...nel.org>
Cc: linux-pci@...r.kernel.org, devicetree@...r.kernel.org,
 linux-arm-kernel@...ts.infradead.org, linux-samsung-soc@...r.kernel.org,
 linux-kernel@...r.kernel.org, linux-phy@...ts.infradead.org,
 linux-fsd@...la.com, mani@...nel.org, lpieralisi@...nel.org, kw@...ux.com,
 bhelgaas@...gle.com, jingoohan1@...il.com, krzk+dt@...nel.org,
 conor+dt@...nel.org, alim.akhtar@...sung.com, vkoul@...nel.org,
 kishon@...nel.org, arnd@...db.de, m.szyprowski@...sung.com,
 jh80.chung@...sung.com
Subject: Re: [PATCH v2 07/10] dt-bindings: phy: Add PHY bindings support for
 FSD SoC

On 04/07/2025 15:09, Pankaj Dubey wrote:
> 
> 
>> -----Original Message-----
>> From: Krzysztof Kozlowski <krzk@...nel.org>
>> Sent: Thursday, July 3, 2025 1:48 AM
>> To: Shradha Todi <shradha.t@...sung.com>; 'Rob Herring'
>> <robh@...nel.org>
>> Cc: linux-pci@...r.kernel.org; devicetree@...r.kernel.org; linux-arm-
>> kernel@...ts.infradead.org; linux-samsung-soc@...r.kernel.org; linux-
>> kernel@...r.kernel.org; linux-phy@...ts.infradead.org; linux-fsd@...la.com;
>> mani@...nel.org; lpieralisi@...nel.org; kw@...ux.com;
>> bhelgaas@...gle.com; jingoohan1@...il.com; krzk+dt@...nel.org;
>> conor+dt@...nel.org; alim.akhtar@...sung.com; vkoul@...nel.org;
>> kishon@...nel.org; arnd@...db.de; m.szyprowski@...sung.com;
>> jh80.chung@...sung.com; pankaj.dubey@...sung.com
>> Subject: Re: [PATCH v2 07/10] dt-bindings: phy: Add PHY bindings support for
>> FSD SoC
>>
>> On 01/07/2025 15:35, Shradha Todi wrote:
>>>>> does not support auto adaptation so we need to tune the PHYs
>>>>> according to the use case (considering channel loss, etc). This is
>>>>> why we
>>>>
>>>> So not same? Decide. Either it is same or not, cannot be both.
>>>>
>>>> If you mean that some wiring is different on the board, then how does
>>>> it differ in soc thus how it is per-soc property? If these are
>>>> use-cases, then how is even suitable for DT?
>>>>
>>>> I use your Tesla FSD differently and then I exchange DTSI and compatibles?
>>>>
>>>> You are no describing real problem and both binding and your
>>>> explanations are vague and imprecise. Binding tells nothing about it,
>>>> so it is example of skipping important decisions.
>>>>
>>>>> have 2 different SW PHY initialization sequence depending on the
>>>>> instance number. Do you think having different compatible (something
>>>>> like
>>>>> tesla,fsd-pcie-phy0 and tesla,fsd-pcie-phy1) and having phy ID as
>>>>> platform data is okay in this case? I actually took reference from files like:
>>>>
>>>> And in different use case on same soc you are going to reverse
>>>> compatibles or instance IDs?
>>>>
>>>
>>> Even though both the PHYs are exactly identical in terms of hardware,
>>> they need to be programmed/initialized/configured differently.
>>>
>>> Sorry for my misuse of the word "use-case". To clarify, these
>>> configurations will always remain the same for FSD SoC even if you use it
>> differently.
>>>
>>> I will use different compatibles for them as I understand that it is
>>> the best option.
>>
>> I still do not see the difference in hardware explained.
>>
> 
> Hi Krzysztof 
> 
> Let me add more details and see if that makes sense to understand the intention
> behind the current design of the PHY driver.
> 
> In FSD SoC, the two PHY instances, although having identical hardware design and
> register maps, are placed in different locations (Placement and routing) inside the
> SoC and have distinct PHY-to-Controller topologies. 
> 
> One instance is connected to two PCIe controllers, while the other is connected to
> only one. As a result, they experience different analog environments, including
> varying channel losses and noise profiles.
> 
> Since these PHYs lack internal adaptation mechanisms and f/w based tuning,
> manual register programming is required for analog tuning, such as equalization,
> de-emphasis, and gain. To ensure optimal signal integrity, it is essential to use different
> register values for each PHY instance, despite their identical hardware design.
> This is because the same register values may not be suitable for both instances due to
> their differing environments and topologies.
> 
> Do let us know if this explains the intention behind separate programming sequence
> for both instance of the PHY?
Thanks, it explains and it should be in binding description if you go
with different compatible, but you should first check if existing
properties do not describe these differences enough, e.g. num-lanes,
max-link-speed.

equalization has its own properties for example.

Best regards,
Krzysztof