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Message-ID: <20250706-diamond-crab-of-will-72205e@krzk-bin>
Date: Sun, 6 Jul 2025 11:44:19 +0200
From: Krzysztof Kozlowski <krzk@...nel.org>
To: Pritam Manohar Sutar <pritam.sutar@...sung.com>
Cc: vkoul@...nel.org, kishon@...nel.org, robh@...nel.org,
krzk+dt@...nel.org, conor+dt@...nel.org, alim.akhtar@...sung.com,
andre.draszik@...aro.org, peter.griffin@...aro.org, neil.armstrong@...aro.org,
kauschluss@...root.org, ivo.ivanov.ivanov1@...il.com, m.szyprowski@...sung.com,
s.nawrocki@...sung.com, linux-phy@...ts.infradead.org, devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
linux-samsung-soc@...r.kernel.org, rosa.pila@...sung.com, dev.tailor@...sung.com,
faraz.ata@...sung.com, muhammed.ali@...sung.com, selvarasu.g@...sung.com
Subject: Re: [PATCH v4 5/6] dt-bindings: phy: samsung,usb3-drd-phy: add
ExynosAutov920 combo SS phy
On Tue, Jul 01, 2025 at 05:37:05PM +0530, Pritam Manohar Sutar wrote:
> This phy supports USB3.1 SSP+(10Gbps) protocol and is backwards
Agian, this?
> compatible to the USB3.0 SS(5Gbps). 'Add-on USB2.0' phy is required
> to support USB2.0 HS(480Mbps), FS(12Mbps) and LS(1.5Mbps) data rates.
> These two phys are combined to form a combo phy.
>
> Add a dedicated compatible string for USB combo SS phy found in this
> SoC. The SoC requires two clocks, named "phy" and "ref" and various
> power supplies (regulators) for the internal circuitry to work.
> The required voltages are:
> * avdd075_usb - 0.75v
> * avdd18_usb20 - 1.8v
> * avdd33_usb20 - 3.3v
One more commitm message completely copy-pasted and completely
uninforming. The voltages are irrelevant. Explain the architecture. This
should be just one patch with proper full description.
>
> Add schema only for 'USB3.1 SSP+' SS phy in this commit.
Why only? Add everything, describe everything, but not what voltages you
have there but the architecture of the PHY.
Best regards,
Krzysztof
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