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Message-ID: <20250708154810.GA2146917@bhelgaas>
Date: Tue, 8 Jul 2025 10:48:10 -0500
From: Bjorn Helgaas <helgaas@...nel.org>
To: Hongxing Zhu <hongxing.zhu@....com>
Cc: "mani@...nel.org" <mani@...nel.org>, Frank Li <frank.li@....com>,
"l.stach@...gutronix.de" <l.stach@...gutronix.de>,
"lpieralisi@...nel.org" <lpieralisi@...nel.org>,
"kwilczynski@...nel.org" <kwilczynski@...nel.org>,
"robh@...nel.org" <robh@...nel.org>,
"bhelgaas@...gle.com" <bhelgaas@...gle.com>,
"shawnguo@...nel.org" <shawnguo@...nel.org>,
"s.hauer@...gutronix.de" <s.hauer@...gutronix.de>,
"kernel@...gutronix.de" <kernel@...gutronix.de>,
"festevam@...il.com" <festevam@...il.com>,
"linux-pci@...r.kernel.org" <linux-pci@...r.kernel.org>,
"linux-arm-kernel@...ts.infradead.org" <linux-arm-kernel@...ts.infradead.org>,
"imx@...ts.linux.dev" <imx@...ts.linux.dev>,
"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH v2] PCI: imx6: Correct the epc_features of i.MX8M chips
On Tue, Jul 08, 2025 at 07:34:57AM +0000, Hongxing Zhu wrote:
> > -----Original Message-----
> > From: Bjorn Helgaas <helgaas@...nel.org>
> ...
> > On Tue, Jun 17, 2025 at 03:34:41PM +0800, Richard Zhu wrote:
> > > i.MX8MQ PCIes have three 64-bit BAR0/2/4 capable and
> > > programmable BARs. But i.MX8MM and i.MX8MP PCIes only have
> > > BAR0/BAR2 64bit programmable BARs, and one 256 bytes size fixed
> > > BAR4.
> > >
> > > Correct the epc_features for i.MX8MM and i.MX8MP PCIes here.
> > > i.MX8MQ is the same as i.MX8QXP, so set i.MX8MQ's epc_features
> > > to imx8q_pcie_epc_features.
> > >
> > > Fixes: 75c2f26da03f ("PCI: imx6: Add i.MX PCIe EP mode support")
> > > Signed-off-by: Richard Zhu <hongxing.zhu@....com>
> > > Reviewed-by: Frank Li <Frank.Li@....com>
> >
> > "Correct the epc_features" doesn't include any specific
> > information, and it's hard to extract the changes for a device
> > from the commit log.
> >
> > This is really two fixes that should be separated so the commit
> > logs can be specific:
>
> Yes, it's right.
> Since it's just one line change for i.MX8MQ. So, I combine the changes into
> this commit for i.MX8M chips.
I want to split them to make it easy for users to understand which
changes are relevant to them. E.g., I have an i.MX8MQ system; do I
need this change and what does it mean for me? Is it going to fix a
problem I've been seeing?
> > - For IMX8MQ_EP, use imx8q_pcie_epc_features (64-bit BARs 0, 2, 4)
> > instead of imx8m_pcie_epc_features (64-bit BARs 0, 2).
> >
> > - For IMX8MM_EP and IMX8MP_EP, add fixed 256-byte BAR 4 in
> > imx8m_pcie_epc_features.
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