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Message-Id: <20250708065242.26371-1-nick.hu@sifive.com>
Date: Tue, 8 Jul 2025 14:52:42 +0800
From: Nick Hu <nick.hu@...ive.com>
To: Paul Walmsley <paul.walmsley@...ive.com>,
Palmer Dabbelt <palmer@...ive.com>,
Conor Dooley <conor@...nel.org>,
linux-riscv@...ts.infradead.org,
devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org
Cc: Nick Hu <nick.hu@...ive.com>,
Rob Herring <robh+dt@...nel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
Palmer Dabbelt <palmer@...belt.com>,
Albert Ou <aou@...s.berkeley.edu>
Subject: [PATCH] dt-bindings: riscv: Add SiFive vendor extensions description
Add description for SiFive vendor extensions "xsfcflushdlone",
"xsfpgflushdlone" and "xsfcease".
Signed-off-by: Nick Hu <nick.hu@...ive.com>
---
.../devicetree/bindings/riscv/extensions.yaml | 18 ++++++++++++++++++
1 file changed, 18 insertions(+)
diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Documentation/devicetree/bindings/riscv/extensions.yaml
index 72c1b063fdfe..10c37c61243d 100644
--- a/Documentation/devicetree/bindings/riscv/extensions.yaml
+++ b/Documentation/devicetree/bindings/riscv/extensions.yaml
@@ -626,6 +626,24 @@ properties:
https://www.andestech.com/wp-content/uploads/AX45MP-1C-Rev.-5.0.0-Datasheet.pdf
# SiFive
+ - const: xsfcease
+ description:
+ SiFive CEASE Instruction Extensions Specification.
+ See more details in
+ https://www.sifive.com/document-file/freedom-u740-c000-manual
+
+ - const: xsfcflushdlone
+ description:
+ SiFive L1D Cache Flush Instruction Extensions Specification.
+ See more details in
+ https://www.sifive.com/document-file/freedom-u740-c000-manual
+
+ - const: xsfpgflushdlone
+ description:
+ SiFive PGFLUSH Instruction Extensions for the power management. The
+ CPU will flush the L1D and enter the cease state after executing
+ the instruction.
+
- const: xsfqmaccdod
description:
SiFive Int8 Matrix Multiplication Extensions Specification.
--
2.17.1
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