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Message-ID:
<PNYPR01MB111711E425806004678041757FE4EA@PNYPR01MB11171.INDPRD01.PROD.OUTLOOK.COM>
Date: Tue, 8 Jul 2025 08:45:50 +0800
From: Chen Wang <unicorn_wang@...look.com>
To: Inochi Amaoto <inochiama@...il.com>, Rob Herring <robh@...nel.org>,
Krzysztof Kozlowski <krzk+dt@...nel.org>, Conor Dooley
<conor+dt@...nel.org>, Paul Walmsley <paul.walmsley@...ive.com>,
Palmer Dabbelt <palmer@...belt.com>, Albert Ou <aou@...s.berkeley.edu>,
Alexandre Ghiti <alex@...ti.fr>
Cc: devicetree@...r.kernel.org, linux-riscv@...ts.infradead.org,
sophgo@...ts.linux.dev, linux-kernel@...r.kernel.org,
Yixun Lan <dlan@...too.org>, Longbin Li <looong.bin@...il.com>
Subject: Re: [PATCH] riscv: dts: sophgo: sg2044: add pmu configuration
On 2025/7/3 8:38, Inochi Amaoto wrote:
> Add PMU configuration for the cpu of sg2044, which is the V2
> version of C920.
>
> Signed-off-by: Inochi Amaoto <inochiama@...il.com>
Reviewed-by: Chen Wang <unicorn_wang@...look.com>
> ---
> arch/riscv/boot/dts/sophgo/sg2044-cpus.dtsi | 91 +++++++++++++++++++++
> 1 file changed, 91 insertions(+)
>
> diff --git a/arch/riscv/boot/dts/sophgo/sg2044-cpus.dtsi b/arch/riscv/boot/dts/sophgo/sg2044-cpus.dtsi
> index 6a35ed8f253c..2d21b2881ab8 100644
> --- a/arch/riscv/boot/dts/sophgo/sg2044-cpus.dtsi
> +++ b/arch/riscv/boot/dts/sophgo/sg2044-cpus.dtsi
> @@ -2778,6 +2778,97 @@ l3_cache: cache-controller-16 {
> };
> };
>
> + pmu {
> + compatible = "riscv,pmu";
> + riscv,event-to-mhpmevent =
> + <0x00003 0x00000000 0x00000010>,
> + <0x00004 0x00000000 0x00000011>,
> + <0x00005 0x00000000 0x00000007>,
> + <0x00006 0x00000000 0x00000006>,
> + <0x00008 0x00000000 0x00000027>,
> + <0x00009 0x00000000 0x00000028>,
> + <0x10000 0x00000000 0x0000000c>,
> + <0x10001 0x00000000 0x0000000d>,
> + <0x10002 0x00000000 0x0000000e>,
> + <0x10003 0x00000000 0x0000000f>,
> + <0x10008 0x00000000 0x00000001>,
> + <0x10009 0x00000000 0x00000002>,
> + <0x10010 0x00000000 0x00000010>,
> + <0x10011 0x00000000 0x00000011>,
> + <0x10012 0x00000000 0x00000012>,
> + <0x10013 0x00000000 0x00000013>,
> + <0x10019 0x00000000 0x00000004>,
> + <0x10021 0x00000000 0x00000003>,
> + <0x10030 0x00000000 0x0000001c>,
> + <0x10031 0x00000000 0x0000001b>;
> + riscv,event-to-mhpmcounters =
> + <0x00003 0x00003 0xfffffff8>,
> + <0x00004 0x00004 0xfffffff8>,
> + <0x00005 0x00005 0xfffffff8>,
> + <0x00006 0x00006 0xfffffff8>,
> + <0x00007 0x00007 0xfffffff8>,
> + <0x00008 0x00008 0xfffffff8>,
> + <0x00009 0x00009 0xfffffff8>,
> + <0x0000a 0x0000a 0xfffffff8>,
> + <0x10000 0x10000 0xfffffff8>,
> + <0x10001 0x10001 0xfffffff8>,
> + <0x10002 0x10002 0xfffffff8>,
> + <0x10003 0x10003 0xfffffff8>,
> + <0x10008 0x10008 0xfffffff8>,
> + <0x10009 0x10009 0xfffffff8>,
> + <0x10010 0x10010 0xfffffff8>,
> + <0x10011 0x10011 0xfffffff8>,
> + <0x10012 0x10012 0xfffffff8>,
> + <0x10013 0x10013 0xfffffff8>,
> + <0x10019 0x10019 0xfffffff8>,
> + <0x10021 0x10021 0xfffffff8>,
> + <0x10030 0x10030 0xfffffff8>,
> + <0x10031 0x10031 0xfffffff8>;
> + riscv,raw-event-to-mhpmcounters =
> + <0x00000000 0x00000001 0xffffffff 0xffffffff 0xfffffff8>,
> + <0x00000000 0x00000002 0xffffffff 0xffffffff 0xfffffff8>,
> + <0x00000000 0x00000003 0xffffffff 0xffffffff 0xfffffff8>,
> + <0x00000000 0x00000004 0xffffffff 0xffffffff 0xfffffff8>,
> + <0x00000000 0x00000005 0xffffffff 0xffffffff 0xfffffff8>,
> + <0x00000000 0x00000006 0xffffffff 0xffffffff 0xfffffff8>,
> + <0x00000000 0x00000007 0xffffffff 0xffffffff 0xfffffff8>,
> + <0x00000000 0x00000008 0xffffffff 0xffffffff 0xfffffff8>,
> + <0x00000000 0x00000009 0xffffffff 0xffffffff 0xfffffff8>,
> + <0x00000000 0x0000000a 0xffffffff 0xffffffff 0xfffffff8>,
> + <0x00000000 0x0000000b 0xffffffff 0xffffffff 0xfffffff8>,
> + <0x00000000 0x0000000c 0xffffffff 0xffffffff 0xfffffff8>,
> + <0x00000000 0x0000000d 0xffffffff 0xffffffff 0xfffffff8>,
> + <0x00000000 0x0000000e 0xffffffff 0xffffffff 0xfffffff8>,
> + <0x00000000 0x0000000f 0xffffffff 0xffffffff 0xfffffff8>,
> + <0x00000000 0x00000010 0xffffffff 0xffffffff 0xfffffff8>,
> + <0x00000000 0x00000011 0xffffffff 0xffffffff 0xfffffff8>,
> + <0x00000000 0x00000012 0xffffffff 0xffffffff 0xfffffff8>,
> + <0x00000000 0x00000013 0xffffffff 0xffffffff 0xfffffff8>,
> + <0x00000000 0x00000014 0xffffffff 0xffffffff 0xfffffff8>,
> + <0x00000000 0x00000015 0xffffffff 0xffffffff 0xfffffff8>,
> + <0x00000000 0x00000016 0xffffffff 0xffffffff 0xfffffff8>,
> + <0x00000000 0x00000017 0xffffffff 0xffffffff 0xfffffff8>,
> + <0x00000000 0x00000018 0xffffffff 0xffffffff 0xfffffff8>,
> + <0x00000000 0x00000019 0xffffffff 0xffffffff 0xfffffff8>,
> + <0x00000000 0x0000001a 0xffffffff 0xffffffff 0xfffffff8>,
> + <0x00000000 0x0000001b 0xffffffff 0xffffffff 0xfffffff8>,
> + <0x00000000 0x0000001c 0xffffffff 0xffffffff 0xfffffff8>,
> + <0x00000000 0x0000001d 0xffffffff 0xffffffff 0xfffffff8>,
> + <0x00000000 0x0000001e 0xffffffff 0xffffffff 0xfffffff8>,
> + <0x00000000 0x0000001f 0xffffffff 0xffffffff 0xfffffff8>,
> + <0x00000000 0x00000020 0xffffffff 0xffffffff 0xfffffff8>,
> + <0x00000000 0x00000021 0xffffffff 0xffffffff 0xfffffff8>,
> + <0x00000000 0x00000022 0xffffffff 0xffffffff 0xfffffff8>,
> + <0x00000000 0x00000023 0xffffffff 0xffffffff 0xfffffff8>,
> + <0x00000000 0x00000024 0xffffffff 0xffffffff 0xfffffff8>,
> + <0x00000000 0x00000025 0xffffffff 0xffffffff 0xfffffff8>,
> + <0x00000000 0x00000026 0xffffffff 0xffffffff 0xfffffff8>,
> + <0x00000000 0x00000027 0xffffffff 0xffffffff 0xfffffff8>,
> + <0x00000000 0x00000028 0xffffffff 0xffffffff 0xfffffff8>,
> + <0x00000000 0x00000029 0xffffffff 0xffffffff 0xfffffff8>,
> + <0x00000000 0x0000002a 0xffffffff 0xffffffff 0xfffffff8>;
> + };
> +
> soc {
> intc: interrupt-controller@...0000000 {
> compatible = "sophgo,sg2044-plic", "thead,c900-plic";
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