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Message-ID: <4dpwzfoh3lkhffe3jtihjyqvqe3nyncl4uvjhw2ctpeid7poa3@igim7botbr3f>
Date: Tue, 8 Jul 2025 13:33:07 +0530
From: Manivannan Sadhasivam <mani@...nel.org>
To: Nitin Rawat <quic_nitirawa@...cinc.com>
Cc: James.Bottomley@...senpartnership.com, martin.petersen@...cle.com, 
	bvanassche@....org, avri.altman@....com, ebiggers@...gle.com, 
	neil.armstrong@...aro.org, konrad.dybcio@....qualcomm.com, linux-arm-msm@...r.kernel.org, 
	linux-kernel@...r.kernel.org, linux-scsi@...r.kernel.org
Subject: Re: [PATCH V2 3/3] scsi: ufs: qcom: Enable QUnipro Internal Clock
 Gating

On Tue, Jul 08, 2025 at 02:33:00AM GMT, Nitin Rawat wrote:
> Enable internal clock gating for QUnipro by setting the following
> attributes to 1 during host controller initialization:
> - DL_VS_CLK_CFG
> - PA_VS_CLK_CFG_REG
> - DME_VS_CORE_CLK_CTRL.DME_HW_CGC_EN
> 
> This change is necessary to support the internal clock gating mechanism
> in Qualcomm UFS host controller.
> 
> Signed-off-by: Nitin Rawat <quic_nitirawa@...cinc.com>
> ---
>  drivers/ufs/host/ufs-qcom.c | 21 +++++++++++++++++++++
>  drivers/ufs/host/ufs-qcom.h |  9 +++++++++
>  2 files changed, 30 insertions(+)
> 
> diff --git a/drivers/ufs/host/ufs-qcom.c b/drivers/ufs/host/ufs-qcom.c
> index dfdc52333a96..25b5f83b049c 100644
> --- a/drivers/ufs/host/ufs-qcom.c
> +++ b/drivers/ufs/host/ufs-qcom.c
> @@ -558,11 +558,32 @@ static int ufs_qcom_power_up_sequence(struct ufs_hba *hba)
>   */
>  static void ufs_qcom_enable_hw_clk_gating(struct ufs_hba *hba)
>  {
> +	int err = 0;
> +

No need to init err.

> +	/* Enable UTP internal clock gating */
>  	ufshcd_rmwl(hba, REG_UFS_CFG2_CGC_EN_ALL, REG_UFS_CFG2_CGC_EN_ALL,
>  		    REG_UFS_CFG2);
> 
>  	/* Ensure that HW clock gating is enabled before next operations */
>  	ufshcd_readl(hba, REG_UFS_CFG2);
> +
> +	/* Enable Unipro internal clock gating */
> +	err = ufshcd_dme_rmw(hba, DL_VS_CLK_CFG_MASK,
> +			     DL_VS_CLK_CFG_MASK, DL_VS_CLK_CFG);
> +	if (err)
> +		goto out;
> +
> +	err = ufshcd_dme_rmw(hba, PA_VS_CLK_CFG_REG_MASK,
> +			     PA_VS_CLK_CFG_REG_MASK, PA_VS_CLK_CFG_REG);
> +	if (err)
> +		goto out;
> +
> +	err = ufshcd_dme_rmw(hba, DME_VS_CORE_CLK_CTRL_DME_HW_CGC_EN,
> +			     DME_VS_CORE_CLK_CTRL_DME_HW_CGC_EN,
> +			     DME_VS_CORE_CLK_CTRL);
> +out:
> +	if (err)
> +		dev_err(hba->dev, "hw clk gating enabled failed\n");

So the error is not a hard fault and you want the driver to continue? If so, it
should be justified in commit message.

- Mani

-- 
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