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Message-ID: <5db9ec69-d0e4-4113-a989-ac75d0f1e5dd@rivosinc.com>
Date: Thu, 10 Jul 2025 16:10:03 +0200
From: Clément Léger <cleger@...osinc.com>
To: Andreas Schwab <schwab@...e.de>
Cc: linux-kernel@...r.kernel.org, linux-kselftest@...r.kernel.org,
linux-riscv@...ts.infradead.org, Palmer Dabbelt <palmer@...belt.com>,
Paul Walmsley <paul.walmsley@...ive.com>, Shuah Khan <shuah@...nel.org>,
Alexandre Ghiti <alex@...ti.fr>
Subject: Re: [PATCH v4] selftests: riscv: add misaligned access testing
On 10/07/2025 15:53, Andreas Schwab wrote:
> On Jul 10 2025, Clément Léger wrote:
>
>> This selftest tests all the currently emulated instructions (except for
>> the RV32 compressed ones which are left as a future exercise for a RV32
>> user). For the FPU instructions, all the FPU registers are tested.
>
> If that didn't catch the missing sign extension that I just fixed in
> <https://lore.kernel.org/linux-riscv/mvmikk0goil.fsf@suse.de>, you
> should consider extending the tests.
>
Hi Andreas, you link doesn't work and I didn't find anything about sign
extension except a patch you wrote for arch_cmpxg().
Thanks,
Clément
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