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Message-ID: <20250710153509.GP1599700@nvidia.com>
Date: Thu, 10 Jul 2025 12:35:09 -0300
From: Jason Gunthorpe <jgg@...dia.com>
To: Jacob Pan <jacob.pan@...ux.microsoft.com>
Cc: Baolu Lu <baolu.lu@...ux.intel.com>, Joerg Roedel <joro@...tes.org>,
	Will Deacon <will@...nel.org>, Robin Murphy <robin.murphy@....com>,
	Kevin Tian <kevin.tian@...el.com>, Jann Horn <jannh@...gle.com>,
	Vasant Hegde <vasant.hegde@....com>,
	Dave Hansen <dave.hansen@...el.com>,
	Alistair Popple <apopple@...dia.com>,
	Peter Zijlstra <peterz@...radead.org>,
	Uladzislau Rezki <urezki@...il.com>,
	Jean-Philippe Brucker <jean-philippe@...aro.org>,
	Andy Lutomirski <luto@...nel.org>, iommu@...ts.linux.dev,
	security@...nel.org, linux-kernel@...r.kernel.org,
	stable@...r.kernel.org
Subject: Re: [PATCH 1/1] iommu/sva: Invalidate KVA range on kernel TLB flush

On Thu, Jul 10, 2025 at 08:28:08AM -0700, Jacob Pan wrote:

> why would IOMMU cache all the entries if the walk is not successful?

Sadly, because nothing in the architecture said not to..

> Also, per x86 vm map how could this example (UUUUS) happen to SVA? i.e.
> sharing intermediate levels.
> 
>  ffffc90000000000 |  -55    TB | ffffe8ffffffffff |   32 TB | vmalloc/ioremap
>  0000000000000000 |    0       | 00007fffffffffff |  128 TB | user-space

Because Linux only uses the leaf U/S bit, the interior bits are set to
not-override the leaf.

Jason

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