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Message-ID: <5998de2a-f3ae-46bf-a975-081da20bab03@kernel.org>
Date: Thu, 10 Jul 2025 09:02:55 +0200
From: Krzysztof Kozlowski <krzk@...nel.org>
To: ksk4725@...sia.com, Jesper Nilsson <jesper.nilsson@...s.com>,
Michael Turquette <mturquette@...libre.com>, Stephen Boyd
<sboyd@...nel.org>, Rob Herring <robh@...nel.org>,
Krzysztof Kozlowski <krzk+dt@...nel.org>, Conor Dooley
<conor+dt@...nel.org>, Sylwester Nawrocki <s.nawrocki@...sung.com>,
Chanwoo Choi <cw00.choi@...sung.com>, Alim Akhtar <alim.akhtar@...sung.com>,
Linus Walleij <linus.walleij@...aro.org>, Tomasz Figa
<tomasz.figa@...il.com>, Catalin Marinas <catalin.marinas@....com>,
Will Deacon <will@...nel.org>, Arnd Bergmann <arnd@...db.de>,
Ravi Patel <ravi.patel@...sung.com>, SungMin Park <smn1196@...sia.com>
Cc: kenkim <kenkim@...sia.com>, Jongshin Park <pjsin865@...sia.com>,
GunWoo Kim <gwk1013@...sia.com>, HaGyeong Kim <hgkim05@...sia.com>,
GyoungBo Min <mingyoungbo@...sia.com>,
Pankaj Dubey <pankaj.dubey@...sung.com>, Shradha Todi
<shradha.t@...sung.com>, Inbaraj E <inbaraj.e@...sung.com>,
Swathi K S <swathi.ks@...sung.com>, Hrishikesh <hrishikesh.d@...sung.com>,
Dongjin Yang <dj76.yang@...sung.com>, Sang Min Kim
<hypmean.kim@...sung.com>, linux-kernel@...r.kernel.org,
linux-arm-kernel@...ts.infradead.org, linux-samsung-soc@...r.kernel.org,
linux-arm-kernel@...s.com, linux-clk@...r.kernel.org,
devicetree@...r.kernel.org, linux-gpio@...r.kernel.org, soc@...ts.linux.dev
Subject: Re: [PATCH 14/16] arm64: dts: axis: Add initial device tree support
On 10/07/2025 02:20, ksk4725@...sia.com wrote:
> From: sungminpark <smn1196@...sia.com>
>
> Add initial device tree support for Axis ARTPEC-8 SoC and Grizzly board.
> This SoC contains four cores of cortex-a53 CPUs and other various
Subject: Initial device tree of what?
> peripheral IPs.
>
> Signed-off-by: Ravi Patel <ravi.patel@...sung.com>
> Signed-off-by: sungminpark <smn1196@...sia.com>
> ---
> MAINTAINERS | 14 ++
> arch/arm64/Kconfig.platforms | 13 +
> arch/arm64/boot/dts/Makefile | 1 +
> arch/arm64/boot/dts/axis/Makefile | 4 +
> arch/arm64/boot/dts/axis/artpec8-grizzly.dts | 67 +++++
> arch/arm64/boot/dts/axis/artpec8.dtsi | 252 +++++++++++++++++++
> 6 files changed, 351 insertions(+)
> create mode 100644 arch/arm64/boot/dts/axis/Makefile
> create mode 100644 arch/arm64/boot/dts/axis/artpec8-grizzly.dts
> create mode 100644 arch/arm64/boot/dts/axis/artpec8.dtsi
>
> diff --git a/MAINTAINERS b/MAINTAINERS
> index fa1e04e87d1d..371005f3f41a 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -2320,6 +2320,20 @@ F: drivers/crypto/axis
> F: drivers/mmc/host/usdhi6rol0.c
> F: drivers/pinctrl/pinctrl-artpec*
>
> +ARM/ARTPEC ARM64 MACHINE SUPPORT
This is samsung soc, so I need a pattern for that as well as I will be
handling patches.
> +M: Jesper Nilsson <jesper.nilsson@...s.com>
> +M: Ravi Patel <ravi.patel@...sung.com>
> +M: SeonGu Kang <ksk4725@...sia.com>
> +M: SungMin Park <smn1196@...sia.com>
Please keep only maintainers who will actually perform reviews of the
code. I am not even sure if this is worth separate entry outside of
Samsung. Please list the IP blocks which are not Samsung here.
> +L: linux-arm-kernel@...ts.infradead.org (moderated for non-subscribers)
> +L: linux-samsung-soc@...r.kernel.org
> +L: linux-arm-kernel@...s.com
> +S: Maintained
> +F: Documentation/devicetree/bindings/clock/axis,artpec*-clock.yaml
> +F: arch/arm64/boot/dts/axis/
> +F: drivers/clk/samsung/clk-artpec*.c
> +F: include/dt-bindings/clock/axis,artpec*-clk.h
> +
> ARM/ASPEED I2C DRIVER
> M: Ryan Chen <ryan_chen@...eedtech.com>
> R: Benjamin Herrenschmidt <benh@...nel.crashing.org>
> diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms
> index 8b76821f190f..418ee47227c1 100644
> --- a/arch/arm64/Kconfig.platforms
> +++ b/arch/arm64/Kconfig.platforms
> @@ -40,6 +40,19 @@ config ARCH_APPLE
> This enables support for Apple's in-house ARM SoC family, such
> as the Apple M1.
>
> +config ARCH_ARTPEC
> + bool "Axis Communications ARTPEC SoC Family"
> + help
> + This enables support for the ARMv8 based ARTPEC SoC Family.
> +
> +config ARCH_ARTPEC8
No, drop. One ARCH symbol.
> + bool "Axis ARTPEC-8 SoC Platform"
> + depends on ARCH_ARTPEC
> + depends on ARCH_EXYNOS
And that's the proof that this is Samsung SoC.
> + select ARM_GIC
> + help
> + This enables support for the Axis ARTPEC-8 SoC.
> +
> menuconfig ARCH_BCM
> bool "Broadcom SoC Support"
>
> diff --git a/arch/arm64/boot/dts/Makefile b/arch/arm64/boot/dts/Makefile
> index 79b73a21ddc2..6b6a3aedc2ed 100644
> --- a/arch/arm64/boot/dts/Makefile
> +++ b/arch/arm64/boot/dts/Makefile
> @@ -9,6 +9,7 @@ subdir-y += amlogic
> subdir-y += apm
> subdir-y += apple
> subdir-y += arm
> +subdir-y += axis
> subdir-y += bitmain
> subdir-y += blaize
> subdir-y += broadcom
> diff --git a/arch/arm64/boot/dts/axis/Makefile b/arch/arm64/boot/dts/axis/Makefile
> new file mode 100644
> index 000000000000..ccf00de64016
> --- /dev/null
> +++ b/arch/arm64/boot/dts/axis/Makefile
> @@ -0,0 +1,4 @@
> +# SPDX-License-Identifier: GPL-2.0
> +
> +dtb-$(CONFIG_ARCH_ARTPEC) += \
> + artpec8-grizzly.dtb
> diff --git a/arch/arm64/boot/dts/axis/artpec8-grizzly.dts b/arch/arm64/boot/dts/axis/artpec8-grizzly.dts
> new file mode 100644
> index 000000000000..7671130a0333
> --- /dev/null
> +++ b/arch/arm64/boot/dts/axis/artpec8-grizzly.dts
> @@ -0,0 +1,67 @@
> +// SPDX-License-Identifier: (GPL-2.0 OR MIT)
> +/*
> + * Axis ARTPEC-8 Grizzly board device tree source
> + *
> + * Copyright (c) 2022-2025 Samsung Electronics Co., Ltd.
> + * https://www.samsung.com
> + * Copyright (c) 2022-2025 Axis Communications AB.
> + * https://www.axis.com
> + */
> +
> +/dts-v1/;
> +#include "artpec8.dtsi"
> +#include <dt-bindings/gpio/gpio.h>
> +/ {
> + model = "ARTPEC-8 grizzly board";
> + compatible = "axis,artpec8-grizzly", "axis,artpec8";
> +
> + aliases {
> + serial0 = &serial_0;
> + };
> +
> + chosen {
> + stdout-path = &serial_0;
> + };
> +
> + memory@...00000 {
> + device_type = "memory";
> + reg = <0x0 0x80000000 0x0 0x80000000>;
> + };
> +};
> +
> +&osc_clk {
> + clock-frequency = <50000000>;
> + status = "okay";
Why?
> +};
> +
> +&serial_0 {
Follow DTS coding style. s > c
o > c
> + status = "okay";
> +};
> +
> +&cmu_cmu {
> + status = "okay";
> +};
> +
> +&cmu_bus {
> + status = "okay";
> +};
> +
> +&cmu_core {
> + status = "okay";
> +};
> +
> +&cmu_cpucl {
> + status = "okay";
> +};
> +
> +&cmu_fsys {
> + status = "okay";
> +};
> +
> +&cmu_imem {
> + status = "okay";
> +};
> +
> +&cmu_peri {
> + status = "okay";
> +};
> diff --git a/arch/arm64/boot/dts/axis/artpec8.dtsi b/arch/arm64/boot/dts/axis/artpec8.dtsi
> new file mode 100644
> index 000000000000..296192560adf
> --- /dev/null
> +++ b/arch/arm64/boot/dts/axis/artpec8.dtsi
> @@ -0,0 +1,252 @@
> +// SPDX-License-Identifier: (GPL-2.0 OR MIT)
> +/*
> + * Axis ARTPEC-8 SoC device tree source
> + *
> + * Copyright (c) 2022-2025 Samsung Electronics Co., Ltd.
> + * https://www.samsung.com
> + * Copyright (c) 2022-2025 Axis Communications AB.
> + * https://www.axis.com
> + */
> +
> +#include <dt-bindings/interrupt-controller/arm-gic.h>
> +#include <dt-bindings/clock/axis,artpec8-clk.h>
> +
> +/ {
> + compatible = "axis,artpec8";
> + interrupt-parent = <&gic>;
> + #address-cells = <2>;
> + #size-cells = <2>;
> +
> + cpus {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + cpu0: cpu@0 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a53";
> + reg = <0x0>;
> + cpu-idle-states = <&cpu_sleep>;
> + enable-method = "psci";
> + clocks = <&cmu_cpucl DOUT_CLK_CPUCL_CPU>;
> + clock-names = "dout_clk_cpucl_cpu";
> + clock-frequency = <1200000000>;
This feels wrong. Frequency changes, doesn't it?
> + };
> +
> + cpu1: cpu@1 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a53";
> + reg = <0x1>;
> + cpu-idle-states = <&cpu_sleep>;
> + enable-method = "psci";
> + clock-frequency = <1200000000>;
> + };
> +
> + cpu2: cpu@2 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a53";
> + reg = <0x2>;
> + cpu-idle-states = <&cpu_sleep>;
> + enable-method = "psci";
> + clock-frequency = <1200000000>;
> + };
> +
> + cpu3: cpu@3 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a53";
> + reg = <0x3>;
> + cpu-idle-states = <&cpu_sleep>;
> + enable-method = "psci";
> + clock-frequency = <1200000000>;
> + };
> +
> + idle-states {
> + entry-method = "psci";
> +
> + cpu_sleep: cpu-sleep {
> + compatible = "arm,idle-state";
> + arm,psci-suspend-param = <0x0010000>;
> + local-timer-stop;
> + entry-latency-us = <300>;
> + exit-latency-us = <1200>;
> + min-residency-us = <2000>;
> + };
> + };
> + };
> +
> + timer {
Also wrongly ordered. See DTS coding style.
> + compatible = "arm,armv8-timer";
> + interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
> + <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
> + <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
> + <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
> + };
> +
> + pmu {
> + compatible = "arm,cortex-a53-pmu";
> + interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
> + };
> +
> + psci {
> + compatible = "arm,psci-0.2";
> + method = "smc";
> + };
> +
> + osc_clk: xxti {
clock-xxti
> + compatible = "fixed-clock";
> + clock-output-names = "xxti";
> + #clock-cells = <0>;
> + };
> +
> + fin_pll: fin_pll {
DTS coding style.
> + compatible = "fixed-factor-clock";
> + clocks = <&osc_clk>;
> + #clock-cells = <0>;
> + clock-div = <2>;
> + clock-mult = <1>;
> + clock-output-names = "fin_pll";
> + };
> +
> + soc: soc@0 {
> + compatible = "simple-bus";
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges = <0x0 0x0 0x0 0x17000000>;
DTS coding style.
> +
> + mct@...40000 {
Look at other SoCs first
> + compatible = "samsung,exynos4210-mct";
You just missed two years of development, right? Look at other SoCs.
> + reg = <0x10040000 0x1000>;
> + clocks = <&fin_pll>, <&cmu_imem MOUT_IMEM_ACLK_USER>;
> + clock-names = "fin_pll", "mct";
> + interrupts = <GIC_SPI 455 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 456 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 457 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 459 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 460 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 461 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 463 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>;
> + };
> +
> + gic: interrupt-controller@...01000 {
> + compatible = "arm,gic-400";
> + #interrupt-cells = <3>;
> + #address-cells = <0>;
> + interrupt-controller;
> + reg = <0x10201000 0x00001000>,
> + <0x10202000 0x00002000>,
> + <0x10204000 0x00002000>,
> + <0x10206000 0x00002000>;
DTS coding style.
> + };
> +
> + cmu_cmu: clock-controller@...00000 {
> + compatible = "axis,artpec8-cmu-cmu";
> + reg = <0x12400000 0x4000>;
> + #clock-cells = <1>;
> + clocks = <&fin_pll>;
> + clock-names = "fin_pll";
> + status = "disabled";
Why? No, don't do that, even if clock frequency of xxti is missing. Look
at other SoCs.
> + };
> +
> + cmu_bus: clock-controller@...10000 {
> + compatible = "axis,artpec8-cmu-bus";
> + reg = <0x12c10000 0x4000>;
> + #clock-cells = <1>;
> + clocks = <&fin_pll>,
> + <&cmu_cmu DOUT_CLKCMU_BUS_BUS>,
> + <&cmu_cmu DOUT_CLKCMU_BUS_DLP>;
> + clock-names = "fin_pll",
> + "dout_clkcmu_bus_bus",
> + "dout_clkcmu_bus_dlp";
> + status = "disabled";
> + };
> +
> + cmu_core: clock-controller@...10000 {
> + compatible = "axis,artpec8-cmu-core";
> + reg = <0x12410000 0x4000>;
> + #clock-cells = <1>;
> + clocks = <&fin_pll>,
> + <&cmu_cmu DOUT_CLKCMU_CORE_MAIN>,
> + <&cmu_cmu DOUT_CLKCMU_CORE_DLP>;
> + clock-names = "fin_pll",
> + "dout_clkcmu_core_main",
> + "dout_clkcmu_core_dlp";
> + status = "disabled";
> + };
> +
> + cmu_cpucl: clock-controller@...10000 {
> + compatible = "axis,artpec8-cmu-cpucl";
> + reg = <0x11410000 0x4000>;
> + #clock-cells = <1>;
> + clocks = <&fin_pll>,
> + <&cmu_cmu DOUT_CLKCMU_CPUCL_SWITCH>;
> + clock-names = "fin_pll",
> + "dout_clkcmu_cpucl_switch";
> + status = "disabled";
> + };
> +
> + cmu_fsys: clock-controller@...10000 {
> + compatible = "axis,artpec8-cmu-fsys";
> + reg = <0x16c10000 0x4000>;
> + #clock-cells = <1>;
> + clocks = <&fin_pll>,
> + <&cmu_cmu DOUT_CLKCMU_FSYS_SCAN0>,
> + <&cmu_cmu DOUT_CLKCMU_FSYS_SCAN1>,
> + <&cmu_cmu DOUT_CLKCMU_FSYS_BUS>,
> + <&cmu_cmu DOUT_CLKCMU_FSYS_IP>;
> + clock-names = "fin_pll",
> + "dout_clkcmu_fsys_scan0",
> + "dout_clkcmu_fsys_scan1",
> + "dout_clkcmu_fsys_bus",
> + "dout_clkcmu_fsys_ip";
> + status = "disabled";
> + };
> +
> + cmu_imem: clock-controller@...10000 {
DTS coding style.
Best regards,
Krzysztof
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