linux-kernel - [PATCH V2 0/2] riscv: errata: Add ERRATA_THEAD_WRITE

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Message-Id: <20250713155321.2064856-1-guoren@kernel.org>
Date: Sun, 13 Jul 2025 11:53:19 -0400
From: guoren@...nel.org
To: palmer@...belt.com,
	guoren@...nel.org,
	conor@...nel.org,
	alexghiti@...osinc.com,
	paul.walmsley@...ive.com,
	bjorn@...osinc.com,
	eobras@...hat.com,
	corbet@....net,
	peterlin@...estech.com,
	rabenda.cn@...il.com
Cc: linux-riscv@...ts.infradead.org,
	linux-kernel@...r.kernel.org
Subject: [PATCH V2 0/2] riscv: errata: Add ERRATA_THEAD_WRITE_ONCE fixup

From: "Guo Ren (Alibaba DAMO Academy)" <guoren@...nel.org>

The early version of XuanTie C9xx cores has a store merge buffer
delay problem. The store merge buffer could improve the store queue
performance by merging multi-store requests, but when there are not
continued store requests, the prior single store request would be
waiting in the store queue for a long time. That would cause
significant problems for communication between multi-cores. This
problem was found on sg2042 & th1520 platforms with the qspinlock
lock torture test.

Changelog:
V2:
 - Add new header file for errata_list_vendors.
 - Rebase newest kernel version.

V1:
https://lore.kernel.org/all/20241214143039.4139398-1-guoren@kernel.org/

Guo Ren (Alibaba DAMO Academy) (2):
  riscv: Move vendor errata definitions to new header
  riscv: errata: Add ERRATA_THEAD_WRITE_ONCE fixup

 arch/riscv/Kconfig.errata                    | 17 ++++++++++
 arch/riscv/errata/thead/errata.c             | 20 ++++++++++++
 arch/riscv/include/asm/errata_list.h         | 19 +----------
 arch/riscv/include/asm/errata_list_vendors.h | 25 ++++++++++++++
 arch/riscv/include/asm/rwonce.h              | 34 ++++++++++++++++++++
 include/asm-generic/rwonce.h                 |  2 ++
 6 files changed, 99 insertions(+), 18 deletions(-)
 create mode 100644 arch/riscv/include/asm/errata_list_vendors.h
 create mode 100644 arch/riscv/include/asm/rwonce.h

-- 
2.40.1