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Message-ID: <20250715160524.3088594-1-quic_pkambar@quicinc.com>
Date: Tue, 15 Jul 2025 21:35:24 +0530
From: Palash Kambar <quic_pkambar@...cinc.com>
To: <mani@...nel.org>, <James.Bottomley@...senPartnership.com>,
<martin.petersen@...cle.com>
CC: <linux-arm-msm@...r.kernel.org>, <linux-scsi@...r.kernel.org>,
<linux-kernel@...r.kernel.org>, <quic_nitirawa@...cinc.com>,
Palash Kambar
<quic_pkambar@...cinc.com>
Subject: [PATCH] ufs: ufs-qcom: disable lane clocks during phy hibern8
The UFS lane clocks ensure that the PHY is adequately powered and
synchronized before initiating the link. Currently, these clocks
remain enabled even after the link enters the Hibern8 state and
are only turned off during runtime or system suspend.
Modify the behavior to disable the lane clocks immediately after
the link transitions to Hibern8, thereby reducing the power
consumption.
Signed-off-by: Palash Kambar <quic_pkambar@...cinc.com>
---
drivers/ufs/host/ufs-qcom.c | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/drivers/ufs/host/ufs-qcom.c b/drivers/ufs/host/ufs-qcom.c
index 318dca7fe3d7..50e174d9b406 100644
--- a/drivers/ufs/host/ufs-qcom.c
+++ b/drivers/ufs/host/ufs-qcom.c
@@ -1141,6 +1141,13 @@ static int ufs_qcom_setup_clocks(struct ufs_hba *hba, bool on,
case PRE_CHANGE:
if (on) {
ufs_qcom_icc_update_bw(host);
+ if (ufs_qcom_is_link_hibern8(hba)) {
+ err = ufs_qcom_enable_lane_clks(host);
+ if (err) {
+ dev_err(hba->dev, "enable lane clks failed, ret=%d\n", err);
+ return err;
+ }
+ }
} else {
if (!ufs_qcom_is_link_active(hba)) {
/* disable device ref_clk */
@@ -1166,6 +1173,9 @@ static int ufs_qcom_setup_clocks(struct ufs_hba *hba, bool on,
if (ufshcd_is_hs_mode(&hba->pwr_info))
ufs_qcom_dev_ref_clk_ctrl(host, true);
} else {
+ if (ufs_qcom_is_link_hibern8(hba))
+ ufs_qcom_disable_lane_clks(host);
+
ufs_qcom_icc_set_bw(host, ufs_qcom_bw_table[MODE_MIN][0][0].mem_bw,
ufs_qcom_bw_table[MODE_MIN][0][0].cfg_bw);
}
--
2.34.1
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