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Message-ID: <20250715034320.2553837-6-jacky_chou@aspeedtech.com>
Date: Tue, 15 Jul 2025 11:43:15 +0800
From: Jacky Chou <jacky_chou@...eedtech.com>
To: <bhelgaas@...gle.com>, <lpieralisi@...nel.org>, <kwilczynski@...nel.org>,
<mani@...nel.org>, <robh@...nel.org>, <krzk+dt@...nel.org>,
<conor+dt@...nel.org>, <joel@....id.au>, <andrew@...econstruct.com.au>,
<linux-aspeed@...ts.ozlabs.org>, <linux-pci@...r.kernel.org>,
<devicetree@...r.kernel.org>, <linux-arm-kernel@...ts.infradead.org>,
<linux-kernel@...r.kernel.org>
CC: <openbmc@...ts.ozlabs.org>, <linux-gpio@...r.kernel.org>,
<linus.walleij@...aro.org>, <p.zabel@...gutronix.de>, <BMC-SW@...eedtech.com>
Subject: [PATCH v2 05/10] ARM: dts: aspeed-g6: Add AST2600 PCIe RC PERST#
Add pinctrl support for PCIe RC PERST#.
Signed-off-by: Jacky Chou <jacky_chou@...eedtech.com>
---
arch/arm/boot/dts/aspeed/aspeed-g6-pinctrl.dtsi | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/arch/arm/boot/dts/aspeed/aspeed-g6-pinctrl.dtsi b/arch/arm/boot/dts/aspeed/aspeed-g6-pinctrl.dtsi
index 289668f051eb..ea879f086c25 100644
--- a/arch/arm/boot/dts/aspeed/aspeed-g6-pinctrl.dtsi
+++ b/arch/arm/boot/dts/aspeed/aspeed-g6-pinctrl.dtsi
@@ -2,6 +2,11 @@
// Copyright 2019 IBM Corp.
&pinctrl {
+ pinctrl_pcierc1_default: pcierc1-default {
+ function = "PCIERC1";
+ groups = "PCIERC1";
+ };
+
pinctrl_adc0_default: adc0_default {
function = "ADC0";
groups = "ADC0";
--
2.43.0
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