linux-kernel - Re: [PATCH 1/3] perf/x86: Add PERF_CAP_PEBS_TIMING

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [day] [month] [year] [list]

Message-ID: <9b4651bf-20e4-406f-ba41-9f67515e5bea@linux.intel.com>
Date: Thu, 17 Jul 2025 17:09:05 +0800
From: "Mi, Dapeng" <dapeng1.mi@...ux.intel.com>
To: Peter Zijlstra <peterz@...radead.org>, Ingo Molnar <mingo@...hat.com>,
 Arnaldo Carvalho de Melo <acme@...nel.org>,
 Namhyung Kim <namhyung@...nel.org>, Sean Christopherson <seanjc@...gle.com>,
 Paolo Bonzini <pbonzini@...hat.com>, Ian Rogers <irogers@...gle.com>,
 Adrian Hunter <adrian.hunter@...el.com>,
 Alexander Shishkin <alexander.shishkin@...ux.intel.com>,
 Kan Liang <kan.liang@...ux.intel.com>, Andi Kleen <ak@...ux.intel.com>,
 Eranian Stephane <eranian@...gle.com>
Cc: kvm@...r.kernel.org, linux-kernel@...r.kernel.org,
 linux-perf-users@...r.kernel.org, Dapeng Mi <dapeng1.mi@...el.com>,
 Yi Lai <yi1.lai@...el.com>
Subject: Re: [PATCH 1/3] perf/x86: Add PERF_CAP_PEBS_TIMING_INFO flag

Run basic perf  counting, PMI based sampling and PEBS based sampling on
Intel Sapphire Rapids, Granite Rapids and Sierra Forest platforms, no issue
is found.

On 7/17/2025 5:03 PM, Dapeng Mi wrote:
> IA32_PERF_CAPABILITIES.PEBS_TIMING_INFO[bit 17] is introduced to
> indicate whether timed PEBS is supported. Timed PEBS adds a new "retired
> latency" field in basic info group to show the timing info. Please find
> detailed information about timed PEBS in section 8.4.1 "Timed Processor
> Event Based Sampling" of "Intel Architecture Instruction Set Extensions
> and Future Features".
>
> This patch adds PERF_CAP_PEBS_TIMING_INFO flag and KVM module leverages
> this flag to expose timed PEBS feature to guest.
>
> Moreover, opportunistically refine the indents and make the macros
> share consistent indents.
>
> Signed-off-by: Dapeng Mi <dapeng1.mi@...ux.intel.com>
> Tested-by: Yi Lai <yi1.lai@...el.com>
> ---
>  arch/x86/include/asm/msr-index.h       | 14 ++++++++------
>  tools/arch/x86/include/asm/msr-index.h | 14 ++++++++------
>  2 files changed, 16 insertions(+), 12 deletions(-)
>
> diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h
> index b7dded3c8113..48b7ed28718c 100644
> --- a/arch/x86/include/asm/msr-index.h
> +++ b/arch/x86/include/asm/msr-index.h
> @@ -315,12 +315,14 @@
>  #define PERF_CAP_PT_IDX			16
>  
>  #define MSR_PEBS_LD_LAT_THRESHOLD	0x000003f6
> -#define PERF_CAP_PEBS_TRAP             BIT_ULL(6)
> -#define PERF_CAP_ARCH_REG              BIT_ULL(7)
> -#define PERF_CAP_PEBS_FORMAT           0xf00
> -#define PERF_CAP_PEBS_BASELINE         BIT_ULL(14)
> -#define PERF_CAP_PEBS_MASK	(PERF_CAP_PEBS_TRAP | PERF_CAP_ARCH_REG | \
> -				 PERF_CAP_PEBS_FORMAT | PERF_CAP_PEBS_BASELINE)
> +#define PERF_CAP_PEBS_TRAP		BIT_ULL(6)
> +#define PERF_CAP_ARCH_REG		BIT_ULL(7)
> +#define PERF_CAP_PEBS_FORMAT		0xf00
> +#define PERF_CAP_PEBS_BASELINE		BIT_ULL(14)
> +#define PERF_CAP_PEBS_TIMING_INFO	BIT_ULL(17)
> +#define PERF_CAP_PEBS_MASK		(PERF_CAP_PEBS_TRAP | PERF_CAP_ARCH_REG | \
> +					 PERF_CAP_PEBS_FORMAT | PERF_CAP_PEBS_BASELINE | \
> +					 PERF_CAP_PEBS_TIMING_INFO)
>  
>  #define MSR_IA32_RTIT_CTL		0x00000570
>  #define RTIT_CTL_TRACEEN		BIT(0)
> diff --git a/tools/arch/x86/include/asm/msr-index.h b/tools/arch/x86/include/asm/msr-index.h
> index b7dded3c8113..48b7ed28718c 100644
> --- a/tools/arch/x86/include/asm/msr-index.h
> +++ b/tools/arch/x86/include/asm/msr-index.h
> @@ -315,12 +315,14 @@
>  #define PERF_CAP_PT_IDX			16
>  
>  #define MSR_PEBS_LD_LAT_THRESHOLD	0x000003f6
> -#define PERF_CAP_PEBS_TRAP             BIT_ULL(6)
> -#define PERF_CAP_ARCH_REG              BIT_ULL(7)
> -#define PERF_CAP_PEBS_FORMAT           0xf00
> -#define PERF_CAP_PEBS_BASELINE         BIT_ULL(14)
> -#define PERF_CAP_PEBS_MASK	(PERF_CAP_PEBS_TRAP | PERF_CAP_ARCH_REG | \
> -				 PERF_CAP_PEBS_FORMAT | PERF_CAP_PEBS_BASELINE)
> +#define PERF_CAP_PEBS_TRAP		BIT_ULL(6)
> +#define PERF_CAP_ARCH_REG		BIT_ULL(7)
> +#define PERF_CAP_PEBS_FORMAT		0xf00
> +#define PERF_CAP_PEBS_BASELINE		BIT_ULL(14)
> +#define PERF_CAP_PEBS_TIMING_INFO	BIT_ULL(17)
> +#define PERF_CAP_PEBS_MASK		(PERF_CAP_PEBS_TRAP | PERF_CAP_ARCH_REG | \
> +					 PERF_CAP_PEBS_FORMAT | PERF_CAP_PEBS_BASELINE | \
> +					 PERF_CAP_PEBS_TIMING_INFO)
>  
>  #define MSR_IA32_RTIT_CTL		0x00000570
>  #define RTIT_CTL_TRACEEN		BIT(0)
>
> base-commit: 829f5a6308ce11c3edaa31498a825f8c41b9e9aa