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Message-Id: <20250717-opp_pcie-v1-0-dde6f452571b@oss.qualcomm.com>
Date: Thu, 17 Jul 2025 19:31:15 +0530
From: Krishna Chaitanya Chundru <krishna.chundru@....qualcomm.com>
To: Viresh Kumar <vireshk@...nel.org>, Nishanth Menon <nm@...com>,
Stephen Boyd <sboyd@...nel.org>,
"Rafael J. Wysocki" <rafael@...nel.org>,
Manivannan Sadhasivam <mani@...nel.org>,
Lorenzo Pieralisi <lpieralisi@...nel.org>,
Krzysztof Wilczyński <kwilczynski@...nel.org>,
Rob Herring <robh@...nel.org>, Bjorn Helgaas <bhelgaas@...gle.com>,
Bjorn Andersson <andersson@...nel.org>,
Konrad Dybcio <konradybcio@...nel.org>,
Krzysztof Kozlowski <krzk+dt@...nel.org>,
Conor Dooley <conor+dt@...nel.org>
Cc: linux-pm@...r.kernel.org, linux-kernel@...r.kernel.org,
linux-pci@...r.kernel.org, linux-arm-msm@...r.kernel.org,
devicetree@...r.kernel.org,
Krishna Chaitanya Chundru <krishna.chundru@....qualcomm.com>
Subject: [PATCH 0/3] opp: Add bw_factor support to adjust bandwidth
dynamically
The existing OPP table in the device tree for PCIe is shared across
different link configurations such as data rates 8GT/s x2 and 16GT/s x1.
These configurations often operate at the same frequency, allowing them
to reuse the same OPP entries. However, 8GT/s and 16 GT/s may have
different characteristics beyond frequency—such as RPMh votes in QCOM
case, which cannot be represented accurately when sharing a single OPP.
To avoid conflicts and duplication in the device tree, we now define only
one set of OPP entries per table and introduce a new mechanism to adjust
bandwidth dynamically using a `bw_factor`.
The `bw_factor` is a multiplier applied to the average and peak bandwidth
values of an OPP entry. This allows PCIe drivers to modify the effective
bandwidth at runtime based on the actual link width without needing
separate OPP entries for each configuration.
Signed-off-by: Krishna Chaitanya Chundru <krishna.chundru@....qualcomm.com>
---
Krishna Chaitanya Chundru (3):
opp: Add bw_factor support to adjust bandwidth dynamically
PCI: qcom: Use bw_factor to adjust bandwidth based on link width
arm64: dts: qcom: sm8450: Keep only x1 lane PCIe OPP entries
arch/arm64/boot/dts/qcom/sm8450.dtsi | 17 ++--------------
drivers/opp/core.c | 37 ++++++++++++++++++++++++++++++++--
drivers/opp/opp.h | 2 ++
drivers/pci/controller/dwc/pcie-qcom.c | 8 ++++++--
include/linux/pm_opp.h | 7 +++++++
5 files changed, 52 insertions(+), 19 deletions(-)
---
base-commit: e2291551827fe5d2d3758c435c191d32b6d1350e
change-id: 20250717-opp_pcie-793160b2b113
Best regards,
--
Krishna Chaitanya Chundru <krishna.chundru@....qualcomm.com>
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