linux-kernel - Re: [RFC PATCH v8 31/35] x86/apic: Handle EOI writes for Secure AVIC guests

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Message-ID: <CAMvTesBVmDRf8j9BD12-_RK5eSELqX8z6_p8whq2rostMNM6JA@mail.gmail.com>
Date: Sun, 20 Jul 2025 12:56:08 +0800
From: Tianyu Lan <ltykernel@...il.com>
To: Neeraj Upadhyay <Neeraj.Upadhyay@....com>
Cc: linux-kernel@...r.kernel.org, bp@...en8.de, tglx@...utronix.de, 
	mingo@...hat.com, dave.hansen@...ux.intel.com, Thomas.Lendacky@....com, 
	nikunj@....com, Santosh.Shukla@....com, Vasant.Hegde@....com, 
	Suravee.Suthikulpanit@....com, David.Kaplan@....com, x86@...nel.org, 
	hpa@...or.com, peterz@...radead.org, seanjc@...gle.com, pbonzini@...hat.com, 
	kvm@...r.kernel.org, kirill.shutemov@...ux.intel.com, huibo.wang@....com, 
	naveen.rao@....com, kai.huang@...el.com
Subject: Re: [RFC PATCH v8 31/35] x86/apic: Handle EOI writes for Secure AVIC guests

On Wed, Jul 9, 2025 at 11:44 AM Neeraj Upadhyay <Neeraj.Upadhyay@....com> wrote:
>
> Secure AVIC accelerates guest's EOI msr writes for edge-triggered
> interrupts.
>
> For level-triggered interrupts, EOI msr writes trigger VC exception
> with SVM_EXIT_AVIC_UNACCELERATED_ACCESS error code. To complete EOI
> handling, the VC exception handler would need to trigger a GHCB protocol
> MSR write event to notify the hypervisor about completion of the
> level-triggered interrupt. Hypervisor notification is required for
> cases like emulated IOAPIC, to complete and clear interrupt in the
> IOAPIC's interrupt state.
>
> However, VC exception handling adds extra performance overhead for
> APIC register writes. In addition, for Secure AVIC, some unaccelerated
> APIC register msr writes are trapped, whereas others are faulted. This
> results in additional complexity in VC exception handling for unacclerated
> APIC msr accesses. So, directly do a GHCB protocol based APIC EOI msr write
> from apic->eoi() callback for level-triggered interrupts.
>
> Use wrmsr for edge-triggered interrupts, so that hardware re-evaluates
> any pending interrupt which can be delivered to guest vCPU. For level-
> triggered interrupts, re-evaluation happens on return from VMGEXIT
> corresponding to the GHCB event for APIC EOI msr write.
>
> Signed-off-by: Neeraj Upadhyay <Neeraj.Upadhyay@....com>
> ---
> Changes since v7:
>  - No change.

Reviewed-by: Tianyu Lan <tiala@...rosoft.com>

-- 
Thanks
Tianyu Lan