linux-kernel - Re: [RFC PATCH v8 33/35] x86/apic: Enable Secure AVIC in Control MSR

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Message-ID: <CAMvTesA_w-pC-aSifCWtWQ1xj5oafNv87YfMtNtqFp6Q3o+D3w@mail.gmail.com>
Date: Sun, 20 Jul 2025 13:47:21 +0800
From: Tianyu Lan <ltykernel@...il.com>
To: Neeraj Upadhyay <Neeraj.Upadhyay@....com>
Cc: linux-kernel@...r.kernel.org, bp@...en8.de, tglx@...utronix.de, 
	mingo@...hat.com, dave.hansen@...ux.intel.com, Thomas.Lendacky@....com, 
	nikunj@....com, Santosh.Shukla@....com, Vasant.Hegde@....com, 
	Suravee.Suthikulpanit@....com, David.Kaplan@....com, x86@...nel.org, 
	hpa@...or.com, peterz@...radead.org, seanjc@...gle.com, pbonzini@...hat.com, 
	kvm@...r.kernel.org, kirill.shutemov@...ux.intel.com, huibo.wang@....com, 
	naveen.rao@....com, kai.huang@...el.com
Subject: Re: [RFC PATCH v8 33/35] x86/apic: Enable Secure AVIC in Control MSR

On Wed, Jul 9, 2025 at 11:45 AM Neeraj Upadhyay <Neeraj.Upadhyay@....com> wrote:
>
> With all the pieces in place now, enable Secure AVIC in Secure
> AVIC Control MSR. Any access to x2APIC MSRs are emulated by
> the hypervisor before Secure AVIC is enabled in the control MSR.
> Post Secure AVIC enablement, all x2APIC MSR accesses (whether
> accelerated by AVIC hardware or trapped as VC exception) operate
> on vCPU's APIC backing page.
>
> Signed-off-by: Neeraj Upadhyay <Neeraj.Upadhyay@....com>
> ---
> Changes since v7:
>  - No change.

Reviewed-by: Tianyu Lan <tiala@...rosoft.com>

-- 
Thanks
Tianyu Lan

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