linux-kernel - Re: [PATCH v2 03/13] dt-bindings: phy: qcom,msm8998-qmp-usb3-phy: support dual TCSR registers

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Message-ID: <2fd202a6-2c92-469c-81c0-8852562d4e35@kernel.org>
Date: Tue, 22 Jul 2025 11:19:59 +0200
From: Krzysztof Kozlowski <krzk@...nel.org>
To: Xiangxu Yin <xiangxu.yin@....qualcomm.com>,
 Rob Clark <robin.clark@....qualcomm.com>, Dmitry Baryshkov
 <lumag@...nel.org>, Abhinav Kumar <abhinav.kumar@...ux.dev>,
 Jessica Zhang <jessica.zhang@....qualcomm.com>, Sean Paul <sean@...rly.run>,
 Marijn Suijten <marijn.suijten@...ainline.org>,
 Maarten Lankhorst <maarten.lankhorst@...ux.intel.com>,
 Maxime Ripard <mripard@...nel.org>, Thomas Zimmermann <tzimmermann@...e.de>,
 David Airlie <airlied@...il.com>, Simona Vetter <simona@...ll.ch>,
 Rob Herring <robh@...nel.org>, Krzysztof Kozlowski <krzk+dt@...nel.org>,
 Conor Dooley <conor+dt@...nel.org>, Kuogee Hsieh <quic_khsieh@...cinc.com>,
 Vinod Koul <vkoul@...nel.org>, Kishon Vijay Abraham I <kishon@...nel.org>
Cc: linux-arm-msm@...r.kernel.org, dri-devel@...ts.freedesktop.org,
 freedreno@...ts.freedesktop.org, devicetree@...r.kernel.org,
 linux-kernel@...r.kernel.org, linux-phy@...ts.infradead.org,
 dmitry.baryshkov@....qualcomm.com, konrad.dybcio@....qualcomm.com,
 fange.zhang@....qualcomm.com, quic_lliu6@...cinc.com,
 quic_yongmou@...cinc.com
Subject: Re: [PATCH v2 03/13] dt-bindings: phy: qcom,msm8998-qmp-usb3-phy:
 support dual TCSR registers

On 22/07/2025 09:22, Xiangxu Yin wrote:
> Add support for specifying two TCSR register addresses in the
> qcom,tcsr-reg property to enable DP-only mode switching. This change
> maintains backward compatibility with the original single-register
> format.
> 
> Also update #clock-cells and #phy-cells to <1> to support clock and PHY
> provider interfaces, respectively. This is required for platforms that
> consume the PHY clock and select PHY mode dynamically.
> 
> Signed-off-by: Xiangxu Yin <xiangxu.yin@....qualcomm.com>
> ---
>  .../bindings/phy/qcom,msm8998-qmp-usb3-phy.yaml    | 28 +++++++++++++++++-----
>  1 file changed, 22 insertions(+), 6 deletions(-)
> 
> diff --git a/Documentation/devicetree/bindings/phy/qcom,msm8998-qmp-usb3-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,msm8998-qmp-usb3-phy.yaml
> index 1636285fbe535c430fdf792b33a5e9c523de323b..badfc46cda6c3a128688ac63b00d97dc2ba742d6 100644
> --- a/Documentation/devicetree/bindings/phy/qcom,msm8998-qmp-usb3-phy.yaml
> +++ b/Documentation/devicetree/bindings/phy/qcom,msm8998-qmp-usb3-phy.yaml
> @@ -44,13 +44,21 @@ properties:
>    vdda-pll-supply: true
>  
>    "#clock-cells":
> -    const: 0
> +    oneOf:
> +      - description: Set to 0 for legacy platforms without clock provider
> +        const: 0
> +      - description: Set to 1 to expose PHY pipe clock.
> +        const: 1
>  
>    clock-output-names:
>      maxItems: 1
>  
>    "#phy-cells":
> -    const: 0
> +    oneOf:
> +      - description: Set to 0 for legacy platforms
> +        const: 0
> +      - description: Set to 1 to supports mode selection (e.g. USB/DP)
> +        const: 1

I don't understand why EXISTING platforms now get more clocks. What did
you change in the hardware? This you must explain in the commit msg.


Best regards,
Krzysztof