linux-kernel - Re: [PATCH v2 1/4] dt-bindings: edac: Add bindings for Xilinx Versal EDAC for XilSem

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Message-ID: <20250723-splendid-brainy-capuchin-cf52e4@kuoka>
Date: Wed, 23 Jul 2025 10:05:59 +0200
From: Krzysztof Kozlowski <krzk@...nel.org>
To: Rama devi Veggalam <rama.devi.veggalam@....com>
Cc: bp@...en8.de, tony.luck@...el.com, michal.simek@....com, 
	robh@...nel.org, krzk+dt@...nel.org, conor+dt@...nel.org, 
	linux-kernel@...r.kernel.org, linux-edac@...r.kernel.org, devicetree@...r.kernel.org, 
	james.morse@....com, mchehab@...nel.org, rric@...nel.org, git@....com
Subject: Re: [PATCH v2 1/4] dt-bindings: edac: Add bindings for Xilinx Versal
 EDAC for XilSem

On Tue, Jul 22, 2025 at 09:33:12PM +0530, Rama devi Veggalam wrote:
> +  Xilinx Versal Soft Error Mitigation (XilSEM) is part of the
> +  Platform Loader and Manager (PLM) which is loaded into and runs on the
> +  Platform Management Controller (PMC). XilSEM is responsible for reporting
> +  and optionally correcting soft errors in Configuration Memory of Versal.
> +  The memory is scanned by a hardware controller in the Versal Programmable
> +  Logic (PL). During the scan, if the controller detects any error, be it
> +  correctable or uncorrectable, it reports the error to PLM. The XilSEM on PLM
> +  performs the error validation and notifies the errors to user application.
> +  This XilSEM EDAC node is responsible for handling error events received from
> +  XilSEM on PLM and also provides an interface to control scan operations and
> +  fetching the scan status & configuration information.
> +
> +properties:
> +  compatible:
> +    const: xlnx,versal-xilsem-edac

Implement or respond to previous comment.

Best regards,
Krzysztof