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Message-ID: <CACRpkdarn16N9637dL=Qo8X8o==7T=wBfHdXPczU=Rv3b270KQ@mail.gmail.com>
Date: Wed, 23 Jul 2025 13:23:11 +0200
From: Linus Walleij <linus.walleij@...aro.org>
To: Jacky Chou <jacky_chou@...eedtech.com>
Cc: bhelgaas@...gle.com, lpieralisi@...nel.org, kwilczynski@...nel.org,
mani@...nel.org, robh@...nel.org, krzk+dt@...nel.org, conor+dt@...nel.org,
joel@....id.au, andrew@...econstruct.com.au, linux-aspeed@...ts.ozlabs.org,
linux-pci@...r.kernel.org, devicetree@...r.kernel.org,
linux-arm-kernel@...ts.infradead.org, linux-kernel@...r.kernel.org,
openbmc@...ts.ozlabs.org, linux-gpio@...r.kernel.org, p.zabel@...gutronix.de,
BMC-SW@...eedtech.com
Subject: Re: [PATCH v2 07/10] pinctrl: aspeed-g6: Add PCIe RC PERST pin group
On Tue, Jul 15, 2025 at 5:43 AM Jacky Chou <jacky_chou@...eedtech.com> wrote:
> The PCIe RC PERST uses SSPRST# as PERST# and enable this pin
> to output.
>
> Signed-off-by: Jacky Chou <jacky_chou@...eedtech.com>
This patch 7/10 applied to the pinctrl tree, why not.
Yours,
Linus Walleij
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