linux-kernel - [PATCH 04/11] riscv: exception handlers can be software guarded transfers

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Message-Id: <20250724-riscv_kcfi-v1-4-04b8fa44c98c@rivosinc.com>
Date: Thu, 24 Jul 2025 16:36:57 -0700
From: Deepak Gupta <debug@...osinc.com>
To: Paul Walmsley <paul.walmsley@...ive.com>, 
 Palmer Dabbelt <palmer@...belt.com>, Albert Ou <aou@...s.berkeley.edu>, 
 Alexandre Ghiti <alex@...ti.fr>, Masahiro Yamada <masahiroy@...nel.org>, 
 Nathan Chancellor <nathan@...nel.org>, 
 Nicolas Schier <nicolas.schier@...ux.dev>, 
 Andrew Morton <akpm@...ux-foundation.org>, 
 David Hildenbrand <david@...hat.com>, 
 Lorenzo Stoakes <lorenzo.stoakes@...cle.com>, 
 "Liam R. Howlett" <Liam.Howlett@...cle.com>, 
 Vlastimil Babka <vbabka@...e.cz>, Mike Rapoport <rppt@...nel.org>, 
 Suren Baghdasaryan <surenb@...gle.com>, Michal Hocko <mhocko@...e.com>, 
 Nick Desaulniers <nick.desaulniers+lkml@...il.com>, 
 Bill Wendling <morbo@...gle.com>, Monk Chiang <monk.chiang@...ive.com>, 
 Kito Cheng <kito.cheng@...ive.com>, Justin Stitt <justinstitt@...gle.com>
Cc: linux-riscv@...ts.infradead.org, linux-kernel@...r.kernel.org, 
 linux-kbuild@...r.kernel.org, linux-mm@...ck.org, llvm@...ts.linux.dev, 
 rick.p.edgecombe@...el.com, broonie@...nel.org, cleger@...osinc.com, 
 samitolvanen@...gle.com, apatel@...tanamicro.com, ajones@...tanamicro.com, 
 conor.dooley@...rochip.com, charlie@...osinc.com, samuel.holland@...ive.com, 
 bjorn@...osinc.com, fweimer@...hat.com, jeffreyalaw@...il.com, 
 heinrich.schuchardt@...onical.com, andrew@...ive.com, ved@...osinc.com, 
 Deepak Gupta <debug@...osinc.com>
Subject: [PATCH 04/11] riscv: exception handlers can be software guarded
 transfers

Exception handlers are static and loaded from readonly memory. Control
transfers can be software guarded and not requiring lpad on target.

Signed-off-by: Deepak Gupta <debug@...osinc.com>
---
 arch/riscv/kernel/entry.S | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/arch/riscv/kernel/entry.S b/arch/riscv/kernel/entry.S
index 598e17e800ae..3f0890b9c0b9 100644
--- a/arch/riscv/kernel/entry.S
+++ b/arch/riscv/kernel/entry.S
@@ -224,12 +224,12 @@ SYM_CODE_START(handle_exception)
 	add t0, t1, t0
 	/* Check if exception code lies within bounds */
 	bgeu t0, t2, 3f
-	REG_L t1, 0(t0)
-2:	jalr t1
+	REG_L t2, 0(t0)
+2:	jalr t2
 	j ret_from_exception
 3:

-	la t1, do_trap_unknown
+	la t2, do_trap_unknown
 	j 2b
 SYM_CODE_END(handle_exception)
 ASM_NOKPROBE(handle_exception)

-- 
2.43.0