linux-kernel - Re: [PATCH 5/8] arm64: dts: s32g2: Add the Software Timer Watchdog (SWT) description

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-ID: <aIp/WrOjYhn61ZPH@lizhi-Precision-Tower-5810>
Date: Wed, 30 Jul 2025 16:23:54 -0400
From: Frank Li <Frank.li@....com>
To: Daniel Lezcano <daniel.lezcano@...aro.org>
Cc: mbrugger@...e.com, chester62515@...il.com,
	ghennadi.procopciuc@....nxp.com, shawnguo@...nel.org,
	s.hauer@...gutronix.de, s32@....com, kernel@...gutronix.de,
	festevam@...il.com, robh@...nel.org, krzk+dt@...nel.org,
	conor+dt@...nel.org, linux-arm-kernel@...ts.infradead.org,
	imx@...ts.linux.dev, devicetree@...r.kernel.org,
	linux-kernel@...r.kernel.org
Subject: Re: [PATCH 5/8] arm64: dts: s32g2: Add the Software Timer Watchdog
 (SWT) description

On Wed, Jul 30, 2025 at 09:50:18PM +0200, Daniel Lezcano wrote:
> Referred in the documentation as the Software Timer Watchdog (SWT),
> the s32g2 has 7 watchdogs. The number of watchdogs is designed to
> allow dedicating one watchdog per Cortex-M7/A53 present on the SoC.
>
> Describe them in the device tree.
>
> Signed-off-by: Daniel Lezcano <daniel.lezcano@...aro.org>
> ---
>  arch/arm64/boot/dts/freescale/s32g2.dtsi | 56 ++++++++++++++++++++++++
>  1 file changed, 56 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/freescale/s32g2.dtsi b/arch/arm64/boot/dts/freescale/s32g2.dtsi
> index 3e775d030e37..12ce02525ae1 100644
> --- a/arch/arm64/boot/dts/freescale/s32g2.dtsi
> +++ b/arch/arm64/boot/dts/freescale/s32g2.dtsi
> @@ -566,5 +566,61 @@ stm6: timer@...24000 {
>  			interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
>  			status = "disabled";
>  		};
> +
> +		swt0: watchdog@...00000 {

keep order according to hex address.

Frank
> +			compatible = "nxp,s32g2-swt";
> +			reg = <0x40100000 0x1000>;
> +			clocks = <&clks 0x3a>, <&clks 0x3b>, <&clks 0x3b>;
> +			clock-names = "counter", "module", "register";
> +			status = "disabled";
> +		};
> +
> +		swt1: watchdog@...04000 {
> +			compatible = "nxp,s32g2-swt";
> +			reg = <0x40104000 0x1000>;
> +			clocks = <&clks 0x3a>, <&clks 0x3b>, <&clks 0x3b>;
> +			clock-names = "counter", "module", "register";
> +			status = "disabled";
> +		};
> +
> +		swt2: watchdog@...08000 {
> +			compatible = "nxp,s32g2-swt";
> +			reg = <0x40108000 0x1000>;
> +			clocks = <&clks 0x3a>, <&clks 0x3b>, <&clks 0x3b>;
> +			clock-names = "counter", "module", "register";
> +			status = "disabled";
> +		};
> +
> +		swt3: watchdog@...0c000 {
> +			compatible = "nxp,s32g2-swt";
> +			reg = <0x4010c000 0x1000>;
> +			clocks = <&clks 0x3a>, <&clks 0x3b>, <&clks 0x3b>;
> +			clock-names = "counter", "module", "register";
> +			status = "disabled";
> +		};
> +
> +		swt4: watchdog@...00000 {
> +			compatible = "nxp,s32g2-swt";
> +			reg = <0x40200000 0x1000>;
> +			clocks = <&clks 0x3a>, <&clks 0x3b>, <&clks 0x3b>;
> +			clock-names = "counter", "module", "register";
> +			status = "disabled";
> +		};
> +
> +		swt5: watchdog@...04000 {
> +			compatible = "nxp,s32g2-swt";
> +			reg = <0x40204000 0x1000>;
> +			clocks = <&clks 0x3a>, <&clks 0x3b>, <&clks 0x3b>;
> +			clock-names = "counter", "module", "register";
> +			status = "disabled";
> +		};
> +
> +		swt6: watchdog@...08000 {
> +			compatible = "nxp,s32g2-swt";
> +			reg = <0x40208000 0x1000>;
> +			clocks = <&clks 0x3a>, <&clks 0x3b>, <&clks 0x3b>;
> +			clock-names = "counter", "module", "register";
> +			status = "disabled";
> +		};
>  	};
>  };
> --
> 2.43.0
>