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Message-Id: <20250730-drm-tidss-field-api-v1-12-a71ae8dd2782@kernel.org>
Date: Wed, 30 Jul 2025 10:57:12 +0200
From: Maxime Ripard <mripard@...nel.org>
To: Jyri Sarha <jyri.sarha@....fi>,
Tomi Valkeinen <tomi.valkeinen@...asonboard.com>,
Maarten Lankhorst <maarten.lankhorst@...ux.intel.com>,
Thomas Zimmermann <tzimmermann@...e.de>, David Airlie <airlied@...il.com>,
Simona Vetter <simona@...ll.ch>
Cc: dri-devel@...ts.freedesktop.org, linux-kernel@...r.kernel.org,
Maxime Ripard <mripard@...nel.org>
Subject: [PATCH 12/14] drm/tidss: dispc: Switch VP_REG_FLD_MOD to using a
mask
The VP_REG_FLD_MOD function takes the start and end bits as parameter
and will generate a mask out of them.
This makes it difficult to share the masks between callers, since we now
need two arguments and to keep them consistent.
Let's change VP_REG_FLD_MOD to take the mask as an argument instead, and
let the caller create the mask. Eventually, this mask will be moved to a
define.
Signed-off-by: Maxime Ripard <mripard@...nel.org>
---
drivers/gpu/drm/tidss/tidss_dispc.c | 29 +++++++++++++++++------------
1 file changed, 17 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/tidss/tidss_dispc.c b/drivers/gpu/drm/tidss/tidss_dispc.c
index 743ceca721691b3944d36bdd5e5fb929d19ab82c..ba843248749d98f08a2393bc54f92f26bba4223d 100644
--- a/drivers/gpu/drm/tidss/tidss_dispc.c
+++ b/drivers/gpu/drm/tidss/tidss_dispc.c
@@ -642,14 +642,14 @@ static u32 VP_REG_GET(struct dispc_device *dispc, u32 vp, u32 idx, u32 mask)
{
return FIELD_GET(mask, dispc_vp_read(dispc, vp, idx));
}
static void VP_REG_FLD_MOD(struct dispc_device *dispc, u32 vp, u32 idx, u32 val,
- u32 start, u32 end)
+ u32 mask)
{
dispc_vp_write(dispc, vp, idx,
- FLD_MOD(dispc_vp_read(dispc, vp, idx), val, GENMASK(start, end)));
+ FLD_MOD(dispc_vp_read(dispc, vp, idx), val, mask));
}
static void OVR_REG_FLD_MOD(struct dispc_device *dispc, u32 ovr, u32 idx,
u32 val, u32 start, u32 end)
{
@@ -1126,11 +1126,12 @@ static void dispc_set_num_datalines(struct dispc_device *dispc,
default:
WARN_ON(1);
v = 3;
}
- VP_REG_FLD_MOD(dispc, hw_videoport, DISPC_VP_CONTROL, v, 10, 8);
+ VP_REG_FLD_MOD(dispc, hw_videoport, DISPC_VP_CONTROL, v,
+ GENMASK(10, 8));
}
static void dispc_enable_am65x_oldi(struct dispc_device *dispc, u32 hw_videoport,
const struct dispc_bus_format *fmt)
{
@@ -1254,16 +1255,18 @@ void dispc_vp_enable(struct dispc_device *dispc, u32 hw_videoport,
dispc_vp_write(dispc, hw_videoport, DISPC_VP_SIZE_SCREEN,
FIELD_PREP(GENMASK(11, 0), mode->hdisplay - 1) |
FIELD_PREP(GENMASK(27, 16), mode->vdisplay - 1));
- VP_REG_FLD_MOD(dispc, hw_videoport, DISPC_VP_CONTROL, 1, 0, 0);
+ VP_REG_FLD_MOD(dispc, hw_videoport, DISPC_VP_CONTROL, 1,
+ GENMASK(0, 0));
}
void dispc_vp_disable(struct dispc_device *dispc, u32 hw_videoport)
{
- VP_REG_FLD_MOD(dispc, hw_videoport, DISPC_VP_CONTROL, 0, 0, 0);
+ VP_REG_FLD_MOD(dispc, hw_videoport, DISPC_VP_CONTROL, 0,
+ GENMASK(0, 0));
}
void dispc_vp_unprepare(struct dispc_device *dispc, u32 hw_videoport)
{
if (dispc->feat->vp_bus_type[hw_videoport] == DISPC_VP_OLDI_AM65X) {
@@ -1280,11 +1283,12 @@ bool dispc_vp_go_busy(struct dispc_device *dispc, u32 hw_videoport)
}
void dispc_vp_go(struct dispc_device *dispc, u32 hw_videoport)
{
WARN_ON(VP_REG_GET(dispc, hw_videoport, DISPC_VP_CONTROL, GENMASK(5, 5)));
- VP_REG_FLD_MOD(dispc, hw_videoport, DISPC_VP_CONTROL, 1, 5, 5);
+ VP_REG_FLD_MOD(dispc, hw_videoport, DISPC_VP_CONTROL, 1,
+ GENMASK(5, 5));
}
enum c8_to_c12_mode { C8_TO_C12_REPLICATE, C8_TO_C12_MAX, C8_TO_C12_MIN };
static u16 c8_to_c12(u8 c8, enum c8_to_c12_mode mode)
@@ -2454,11 +2458,11 @@ static void dispc_vp_init(struct dispc_device *dispc)
dev_dbg(dispc->dev, "%s()\n", __func__);
/* Enable the gamma Shadow bit-field for all VPs*/
for (i = 0; i < dispc->feat->num_vps; i++)
- VP_REG_FLD_MOD(dispc, i, DISPC_VP_CONFIG, 1, 2, 2);
+ VP_REG_FLD_MOD(dispc, i, DISPC_VP_CONFIG, 1, GENMASK(2, 2));
}
static void dispc_initial_config(struct dispc_device *dispc)
{
dispc_plane_init(dispc);
@@ -2687,12 +2691,12 @@ static void dispc_k2g_vp_set_ctm(struct dispc_device *dispc, u32 hw_videoport,
dispc_k2g_cpr_from_ctm(ctm, &cpr);
dispc_k2g_vp_write_csc(dispc, hw_videoport, &cpr);
cprenable = 1;
}
- VP_REG_FLD_MOD(dispc, hw_videoport, DISPC_VP_CONFIG,
- cprenable, 15, 15);
+ VP_REG_FLD_MOD(dispc, hw_videoport, DISPC_VP_CONFIG, cprenable,
+ GENMASK(15, 15));
}
static s16 dispc_S31_32_to_s3_8(s64 coef)
{
u64 sign_bit = 1ULL << 63;
@@ -2753,12 +2757,12 @@ static void dispc_k3_vp_set_ctm(struct dispc_device *dispc, u32 hw_videoport,
dispc_csc_from_ctm(ctm, &csc);
dispc_k3_vp_write_csc(dispc, hw_videoport, &csc);
colorconvenable = 1;
}
- VP_REG_FLD_MOD(dispc, hw_videoport, DISPC_VP_CONFIG,
- colorconvenable, 24, 24);
+ VP_REG_FLD_MOD(dispc, hw_videoport, DISPC_VP_CONFIG, colorconvenable,
+ GENMASK(24, 24));
}
static void dispc_vp_set_color_mgmt(struct dispc_device *dispc,
u32 hw_videoport,
const struct drm_crtc_state *state,
@@ -2905,11 +2909,12 @@ static void dispc_softreset_k2g(struct dispc_device *dispc)
dispc_set_irqenable(dispc, 0);
dispc_read_and_clear_irqstatus(dispc);
spin_unlock_irqrestore(&dispc->tidss->irq_lock, flags);
for (unsigned int vp_idx = 0; vp_idx < dispc->feat->num_vps; ++vp_idx)
- VP_REG_FLD_MOD(dispc, vp_idx, DISPC_VP_CONTROL, 0, 0, 0);
+ VP_REG_FLD_MOD(dispc, vp_idx, DISPC_VP_CONTROL, 0,
+ GENMASK(0, 0));
}
static int dispc_softreset(struct dispc_device *dispc)
{
u32 val;
--
2.50.1
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